| 摘要: | 1200 V 元件所使用之磊晶片為成長於低阻值矽基板上並具有 p 型氮化鎵層之氮
化鋁鎵/氮化鎵異質結構，為了使元件得以承受 1200 V 的崩潰電壓，並且降低來自氮
化鎵與矽基板晶格不匹配之問題，磊晶層中使用的緩衝層厚度達 6.5 μm 並且在該層
中進行碳元素的摻雜，藉此來提升垂直方向的絕緣性。在此磊晶結構上製作加強型氮
化鎵高電子遷移率電晶體並進行討論，除了傳統的 p 型氮化鎵閘極結構之外，同時
製作具源極場板的 p 型氮化鎵閘極結構進行量測。此外也利用 Silvaco TCAD 特性模
擬有無源極場板之元件電場分析。
基板接地之元件崩潰電壓測試中，傳統的 p-GaN gate HEMT (LGD = 20 μm)在汲
極漏電流達 1 mA/mm 時之崩潰電壓為 1755 V、具源極場板之元件為 1759 V，而特徵
導通電阻(RON,sp)則分別為 7.57 mΩ·cm2 以及 7.89 mΩ·cm2。透過對不同電極漏電流的
分析了解崩潰電壓限制主要來自於垂直方向之基板(Isub)漏電流所導致，由於是 Isub 所
主導的崩潰電壓，所以閘極邊緣電場分散的場板結構並無對崩潰達到改善。但進一步
採用基板浮接之崩潰電壓測試中，傳統 p-GaN gate HEMT 在汲極漏電流定達 1
mA/mm 時崩潰電壓可承受 1622 V，而具源極場板之元件則可達 1962 V。透過對漏電
流的分析則可以知道主導崩潰量測的路徑是由閘極(IG)漏電流所主導，且元件具有源
極場板可以得到崩潰電壓改善，了解到閘極漏電流是此研究製作之元件的主要缺失。
最後進行特徵導通電阻組成的分析，利用目前的製程技術和漏電流為基礎估算歐
姆接觸電阻、片電阻以及閘極與汲極距離調整對特徵導通電阻的改善。計算出閘極與
汲極距離縮短之狀況下，以閘極漏電流主導之元件，在元件尺寸 LG = 2 μm、Lp-GaN =
4 μm、LGS = 3 μm、LGD = 11 μm 時，漏電流定義達 1 μA/mm 下，RON,sp 則降為 1.35
mΩ·cm2，預期 1200 V 元件可以達到世界水準。
;The epitaxial layer used in the 1200 V device was grown on a low-resistivity silicon substrate
with a p-GaN layer on top of the AlGaN/GaN heterostructure. To achieve a 1200 V blocking
voltage and mitigate the lattice mismatch issue between GaN and silicon, a 6.5 μm thick
buffer layer with carbon doping was used in the epitaxial structure to enhance vertical
insulation. Enhancement-mode AlGaN/GaN high-electron-mobility transistors (HEMTs)
were fabricated on this epitaxial structure, including both conventional p-GaN gate HEMTs
and p-GaN gate HEMTs with a source field plate (SFP). Electric field analysis of devices
with and without SFP was performed using Silvaco TCAD simulation.
In the grounded substrate off-state blocking voltage measurement, the conventional p-GaN
gate HEMT (LGD = 20 μm) exhibited a blocking voltage of 1755 V at a drain leakage current
of 1 mA/mm, while the device with SFP showed a blocking voltage of 1759 V with RON,sp
values of 7.57 mΩ·cm2
and 7.89 mΩ·cm2
, respectively. Analysis of different leakage
currents revealed that the primary limitation on blocking voltage came from the vertical
substrate (Isub) leakage current. Thus, the source field plate structure, designed to disperse
the gate edge electric field, did not improve the blocking voltage. However, in the floating
substrate off-state blocking voltage measurement, the conventional p-GaN gate HEMT
achieved a blocking voltage of 1622 V at a drain leakage current of 1 mA/mm, while the
device with SFP reached 1962 V. Leakage current analysis indicated that blocking was
predominantly influenced by the gate (IG) leakage current, and the device with the source
field plate exhibited improved blocking voltage. The analysis identified gate leakage current
as the main drawback in the fabricated devices.
Finally, an analysis of the constituent components of specific on-resistance was conducted,
considering current leakage, Ohmic contact resistance, sheet resistance, and gate-to-drain
distance adjustments based on current process technology. By shortening the gate-to-drain
distance in devices dominated by gate leakage current (LG = 2 μm, Lp-GaN = 4 μm, LGS = 3
μm, LGD = 11 μm, and leakage current defining 1 μA/mm), the specific on-resistance (RON,sp)
decreased to 1.35 mΩ·cm2
. This suggests that the 1200 V device can achieve world-class
performance. |
