針對多通道三維隨機存取記憶體之測試和良率增進技術;Testing and Yield-Enhancement Techniques for Multi-Channel 3D DRAMs

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题名:	針對多通道三維隨機存取記憶體之測試和良率增進技術;Testing and Yield-Enhancement Techniques for Multi-Channel 3D DRAMs
作者:	吳冠德;Wu, Kuan-Te
贡献者:	電機工程學系
关键词:	測試;良率增進;多通道;三維隨機存取記憶體;Testing;Yield-Enhancement;Multi-Channel;3D DRAM
日期:	2023-08-21
上传时间:	2024-09-19 17:08:48 (UTC+8)
出版者:	國立中央大學
摘要:	使用穿矽孔三維整合技術提供了許多不同於二維整合技術的好處，像是低功耗、高效能、體積小、異質整合等等。三維整合技術已被廣泛使用在動態隨機存取記憶體中，使其達到更高的記憶體密度和更高的效能。三維動態隨機存取記憶體由多個通道所組成，以提供更寬的資料頻寬；然而，以穿矽孔為基底的三維動態隨機存取記憶體能否量產的兩大關鍵在於其測試及良率。在本文的第一部分，提出了針對多通道維動態隨機存取記憶體其通道間可共享內建式自我測試架構，此內建式自我測試架構能處理多通道間不同讀取和寫入延遲的情況下，同時提供測試圖樣給多通道並且依其回傳的資料判斷其是否有錯，實驗模擬結果顯示，在一個雙通道1G位元的多通道動態隨機存取記憶體，所提出來的內建式自我測試架構與現存的共享內建式自我測試架構來做比較，最高能達到降低11%的測試時間且所付出的面積成本僅有0.003%。在本文的第二部分，我們介紹針對多通道三維動態隨機存取記憶體以點對點匯流排為基底的輸入輸出介面，根據此輸入輸出介面，我們提出錯誤容忍架構，其能容忍在此介面的錯誤瑕疵，如此多通道三維動態隨機存取記憶體的良率便能被提升。提出的錯誤容忍架構是使用通道間重組機制來容忍在輸入輸出介面的穿矽孔和微凸塊其錯誤瑕疵，此外，也提出錯誤演算法來找出在穿矽孔和微凸塊的斷開瑕疵，進一步，我們也針對多通道三維動態隨機存取記憶體設計內建式自我修復電路，其能執行找出錯誤位址的測試演算法並產生重組的控制訊號。分析結果顯示，相較現存的通道間重組架構，我們所提出的錯誤容忍架構能提升良率達23%。我們所實現的內建式自我修復電路是使用TSMC 65nm LP的製程技術來合成，針對16個通道且每個通道的資料寬為128位元的多通道三維動態隨機存取記憶體，我們所提出的架構僅增加0.28%的硬體成本。 ;Three-dimensional (3D) integration technology using through silicon via (TSV) offers many benefits over 2D integration technology, such as low power, high performance, small footprint, heterogeneous integration etc. 3D integration technology has been used to realize dynamic random access memories (DRAMs) that provides higher memory density and higher performance than modern 2D DRAMs. 3D DRAMs typically have multiple channels to provide more data bandwidth. However, testing and yield are two key challenges of the TSV-based3D DRAMs for the volume production. In the first part of the thesis, a channel-shareable built-in self-test (BIST) scheme for multi-channel 3D DRAMs is proposed. The BIST scheme is capable of applying test pat-terns and evaluating test responses for multiple channels simultaneously, regardless of the read/write latency differences among the channels. As a result, the proposed BIST scheme can significantly reduce the test time. The simulation results show that the proposed BIST scheme can achieve about 11% test time reduction compared to the existing shared BIST scheme for a two-channel 1G-bit DRAM, by paying only about 0.003% area cost. In the second part of the thesis, we introduce a point-to-point bus-based IO interface for multi-channel 3D DRAMs. Based on the IO interface, we propose a fault-tolerant scheme to tolerance the defects in IO interface such that the yield of multi-channel 3D DRAMs can be improved. The proposed fault-tolerance scheme uses intra-channel and inter-channel reconfiguration mechanisms to tolerance the defects in TSVs and micro bumps of the IO interface. Also, a fault-location algorithm is proposed to locate the positions of open defects. Furthermore, we design a built-in self-repair (BISR) circuit which can generate the proposed fault-location test algorithm and reconfiguration control signals for 3D DRAMs. Analysis results show that the proposed fault-tolerance scheme can achieve above 23% yield gain compared to the existing inter-channel reconfiguration scheme. The BISR designed with TSMC 65nm LP process technology incurs only about 0.28% hardware overhead for a 3D DRAM with 16 channels in which each channel has 128 bits.
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