本論文證實以 RISC-V 為基礎進行 DDS 通訊協定晶片設計具有可行性與彈性，所提出之加速模組亦可應用於其他邊緣運算場域，如無人載具、感測網路或智慧控制裝置之高效資料傳輸任務。 ;This thesis proposes a system-on-chip (SoC) design based on the RISC-V architecture, implementing the Data Distribution Service (DDS) communication protocol through a hardware/software co-design methodology. The system integrates a modular packet construction control process, including initialization, field encoding, task completion reporting, and state recovery. The packet construction logic is implemented using Verilog HDL, and the control flow is integrated via customized RISC-V instruction sequences.
Simulation and verification are conducted using Quartus II and ModelSim for RTL design, while control software is evaluated using the Venus RISC-V emulator. Experimental results show that the traditional software-based approach requires approximately 32 cycles to complete a single packet construction task. In contrast, the proposed FPGA-based hardware accelerator completes the same task in 25.7 cycles, achieving an 19.7% performance improvement. Furthermore, the adoption of vectorized packaging and non-blocking transmission enhances timing efficiency and reduces logic area consumption, optimizing both latency and hardware resource utilization.
The results demonstrate the feasibility and scalability of implementing DDS communication logic on a RISC-V-based SoC. The proposed design is also applicable to edge computing applications, such as unmanned vehicles, sensor networks, and intelligent control systems that demand high-performance data transmission.
