基於RISC-V架構之DDS通訊協定系統晶片的軟硬體協同設計;HW/SW Co-Design of a DDS Communication Protocol System-on-Chip Based on RISC-V Architecture

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Title:	基於RISC-V架構之DDS通訊協定系統晶片的軟硬體協同設計;HW/SW Co-Design of a DDS Communication Protocol System-on-Chip Based on RISC-V Architecture
Authors:	黃紹宇;Huang, Shao-Yu
Contributors:	通訊工程學系
Keywords:	DDS 通訊協定;RISC-V 架構;硬體加速;系統晶片;DDS Communication Protocol;RISC-V Architecture;Hardware acceleration;System-on-Chip (SoC)
Date:	2025-07-01
Issue Date:	2025-10-17 12:19:37 (UTC+8)
Publisher:	國立中央大學
Abstract:	本研究旨在設計一套基於 RISC-V 架構之 DDS 通訊協定系統晶片，透過軟硬體協同設計方法整合資料封裝控制流程與加速模組，以提升嵌入式通訊系統之效能與可移植性。研究中採用模組化設計策略，將封包建構流程拆分為初始化參數設定、欄位加速封裝處理、任務完成回報與系統狀態回復等子模組，並以 Verilog HDL 實作資料封裝控制單元，搭配 RISC-V 指令集整合控制流程。在實驗部分，系統以 Quartus II 與 ModelSim 進行模擬驗證，並以 Venus 平台進行 RISC-V 控制程式效能測試。結果顯示，傳統 RISC-V 軟體流程執行完整一筆封包建構任務約需 32 個週期（cycle），而本研究設計之 FPGA 加速模組可於 25.7 cycle 內完成同樣任務，效能提升約 19.7%。此外，透過向量封裝與非阻塞式資料傳輸設計，有效降低時序延遲與邏輯資源消耗，達到系統面積與延遲之雙重優化。本論文證實以 RISC-V 為基礎進行 DDS 通訊協定晶片設計具有可行性與彈性，所提出之加速模組亦可應用於其他邊緣運算場域，如無人載具、感測網路或智慧控制裝置之高效資料傳輸任務。 ;This thesis proposes a system-on-chip (SoC) design based on the RISC-V architecture, implementing the Data Distribution Service (DDS) communication protocol through a hardware/software co-design methodology. The system integrates a modular packet construction control process, including initialization, field encoding, task completion reporting, and state recovery. The packet construction logic is implemented using Verilog HDL, and the control flow is integrated via customized RISC-V instruction sequences. Simulation and verification are conducted using Quartus II and ModelSim for RTL design, while control software is evaluated using the Venus RISC-V emulator. Experimental results show that the traditional software-based approach requires approximately 32 cycles to complete a single packet construction task. In contrast, the proposed FPGA-based hardware accelerator completes the same task in 25.7 cycles, achieving an 19.7% performance improvement. Furthermore, the adoption of vectorized packaging and non-blocking transmission enhances timing efficiency and reduces logic area consumption, optimizing both latency and hardware resource utilization. The results demonstrate the feasibility and scalability of implementing DDS communication logic on a RISC-V-based SoC. The proposed design is also applicable to edge computing applications, such as unmanned vehicles, sensor networks, and intelligent control systems that demand high-performance data transmission.
Appears in Collections:	[Graduate Institute of Communication Engineering] Electronic Thesis & Dissertation

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