Graph Neural network被廣泛運用在非歐幾里得數據上，FPGA在硬體電路上的彈性框架，以及SRAM相對較低的耗電適合執行accelertor.過去的研究沒有很好的利用了GNN資料的低依賴度這個特性。在我們的研究中，我們設計了一種SRAM架構，專門處理GNN aggregation的步驟，並透過GNN資料低依賴性的特點，設計了一種基於資料集度數的排程演算法，有效的減少GNN在aggregation中的總操作次數，並同步減少資料在SRAM中經常被搬移而造成的開銷。我們的實驗表明在SRAM adder上，擁有比較好的執行速度，並減少了整體功耗。;Graph Neural Networks (GNNs) have been widely applied to non-Euclidean data structures such as social and molecular graphs. Field-Programmable Gate Arrays (FPGAs), with their flexible hardware configuration and low-power SRAM design, provide an energy-efficient platform for GNN acceleration. However, prior works have not fully exploited the inherent low inter-node dependency in GNN datasets. In this work, we propose a novel SRAM-based architecture tailored for the aggregation phase of GNNs. Leveraging the low dependency property of graph data, we design a degree-aware scheduling algorithm that significantly reduces redundant aggregation operations and minimizes data movement overhead within SRAM. Experimental results show that our FPGA-based SRAM adder achieves faster execution and reduced overall energy consumption compared to baseline designs.
