IEEE Computer Society;Piscataway: IEEE Computer Society
摘要:
摘要： Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channel-based 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes. 其他題名： DTM 出版者： Piscataway: IEEE Computer Society 出版日期： 2016-04-01 出處： IEEE design and test, 2016-04, Vol.33 (2), p.30-39 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016 識別號： ISSN: 2168-2356 識別號： EISSN: 2168-2364 識別號： DOI: 10.1109/MDAT.2015.2455347 識別號： CODEN: IDTCEC
