Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
摘要:
摘要： This paper presents an error tolerance scheme for 3-D CMOS imagers that are constructed by stacking a pixel array of imager sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using microbumps (μbumps) and through silicon vias (TSVs). To deliver high-quality images in the presence of single or multiple μbump, ADC, or TSV failures, we propose to interleave the connections from pixels to ADCs and recover the corrupted data in the ISPs. Key design parameters, such as the interleaving stride and the grouping ratio are determined by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3-D imager from 44% to 97%. 其他題名： TVLSI 出版者： New York, NY: IEEE 出版日期： 2013-03-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2013-03, Vol.21 (3), p.465-474 資源來源： IEEE Electronic Library (IEL) 版權： 2014 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Mar 2013 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2012.2190148 識別號： CODEN: IEVSE9
