本論文遵循USB 3.2 Gen1的通訊規範，實現一個具自適應且多階資料獨立相位追蹤補償技術之5 Gbps半速率時脈與資料回復電路。;In recent years, with the advanced process technology and the increasing demand for product applications, data transmission rates have significantly increase. Nowadays, high-speed serial link has become dominant in transmission interfaces, such as PCI Express, Ethernet, USB, and HDMI. However, as data rates continue to increase and unit interval continue to shrink, jitter becomes the significant issue, and the timing margin in circuits become increasingly constrained, leading to worse jitter tolerance and higher bit error rate. Therefore, reducing hunting jitter and improving jitter tolerance are crucial in circuit design.
This thesis adheres to the USB 3.2 Gen1 communication specification and implements a 5 Gbps half-rate clock and data recovery circuit with adaptive and multi-level data independent phase tracking compensation technology.
