應用於X頻段互補式金氧半導體F類壓控振器與使用動態體偏壓技術B/C類混合式壓控振盪器暨整數型鎖相迴路之研製;Design and Implementation of CMOS X-Band Class-F Voltage-Controlled Oscillator, Dynamic Body Biasing Technique for Class-B/C Hybrid-Mode Voltage-Controlled Oscillator, and Integer-N Phase-Locked Loop

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Title:	應用於X頻段互補式金氧半導體F類壓控振器與使用動態體偏壓技術B/C類混合式壓控振盪器暨整數型鎖相迴路之研製;Design and Implementation of CMOS X-Band Class-F Voltage-Controlled Oscillator, Dynamic Body Biasing Technique for Class-B/C Hybrid-Mode Voltage-Controlled Oscillator, and Integer-N Phase-Locked Loop
Authors:	邱恩芸;Qiu, En-Yun
Contributors:	電機工程學系
Keywords:	壓控振盪器;鎖相迴路;Voltage Controlled Oscillator (VCO);phase-locked loop (PLL)
Date:	2024-11-12
Issue Date:	2025-04-09 17:48:18 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文擬研究收發機中本地振盪源的相關電路，設計應用於X頻段之本地振盪電路，本文首先介紹LC振盪器的振盪條件以及相位雜訊相關的分析與成因，最後介紹所實現的電路，本論文一共實現三種電路，皆使用tsmcTM 0.18 μm互補式金氧半導體製程製作，內容如下所述： I. F類壓控振盪器：本電路實作具有低相位雜訊之F類壓控振盪器，使用變壓器耦合同時實現一、二、三階的共振腔，透過改變輸出波型使其呈現類方波，以此實現F類操作，提升相位雜訊的表現。整體電路經由量測後，在0.7V的直流供應下，電路功耗為9.1 ~ 10.5 mW，可調範圍10.14 ~ 11.45 GHz，頻寬為12.1%，加入線損後量測到的輸出功率為−1.59 ~ −0.2 dBm，相位雜訊在1-MHz偏移頻率下最佳為-115 dBc/Hz，FOM、FOMT分別-185.11 dBc/Hz與-186.79 dBc/Hz，晶片面積包含I/O PAD為0.99 × 0.82 mm2。 II. 使用動態體偏壓技術之B/C類混合式壓控振盪器：本電路實作具有低功耗特性之B/C類混合式壓控振盪器，透過C類高電流效率的操作以及正向體偏壓技術，使壓控振盪器得以實現低功耗的目標，同時再以操作於B類之PMOS電晶體輔助，提高電路振盪的穩定性。在1.1V的直流供應下，電路功耗為2.5 mW，可調頻率範圍10 ~ 10.7 GHz，頻寬為6.7 %，加入線損後的量測輸出功率為−5.3 ~ −8.2 dBm，相位雜訊在1-MHz偏移頻率下最佳為-108.6 dBc/Hz，FOM、FOMT最佳分別-184.7 dBc/Hz與-181.4 dBc/Hz。整體晶片面積包含I/O PAD為0.89 × 0.69 mm2。 III. 使用F類壓控振盪器之X頻段整數型鎖相迴路本電路使用第一顆設計的F類壓控振盪器，實現X頻段的整數型鎖相迴路，電路包含壓控振盪器、電流模式邏輯除頻器、雙轉單緩衝放大器、真單一相位時脈除頻器、全擺幅緩衝器、相位頻率偵測器、電荷幫浦以及迴路濾波器。章節中包含對各個子電路的介紹與數學分析。本次量測到的鎖相迴路鎖定頻寬為9.63 ~ 10.28 GHz，參考頻率在除256模式下為37.64 ~ 40.16 MHz，在除260模式下為37.04 ~ 39.54 MHz，整體功耗約46.8 mW，晶片面積包含I/O PAD為1.2 × 0.95 mm2，在鎖定中心頻10 GHz時量測到的參考突波小於-45 dBc，鎖定後量測到最佳的1-MHz偏移相位雜訊為-96.9dBc/Hz，由10 kHz到40 MHz (SSA儀器量測極限)的時脈抖動為940 fsec。 ;This thesis investigates the designs of the local oscillators for the applications in X-band. In this thesis, we firstly introduce the oscillation condition, analyze the causes of phase noise and finally illustrate the circuit implemented in this thesis. In this thesis, three LO circuits were implemented in tsmcTM 0.18 μm CMOS processes. The developed LO circuits are listed as follow: I. A Class-F Voltage Controlled Oscillator This circuit implements a Class-F voltage-controlled oscillator with low phase noise. It uses transformer coupling to realize the fundamental, second, and third order resonant. By making the output waveform appear like a square wave, Class F operation is achieved. The measurements are listed as below, under a 0.7 V DC supply, the circuit power consumption is 9.1 ~ 10.5 mW, the operation frequency is from 10.14 to 11.45 GHz, (i.e., 12.1% tuning range). After subtracting the cable loss, the measured output power is −1.59 ~ −0.2 dBm, the best phase noise at 1-MHz offset frequency is -115 dBc/Hz, FOM and FOMT are -185.11 dBc/Hz and -186.79 dBc/Hz respectively, the chip area including I/O PAD is 0.99 × 0.82 mm2. II. A dynamic body biasing technique low power consumption on Class-B/C Hybrid-Mode VCO This circuit implements a Class B/C hybrid voltage-controlled oscillator with low power consumption. Through Class-C high current efficiency operation and forward body biasing technique, the voltage-controlled oscillator can achieve the goal of low power consumption. And PMOS auxiliary oscillation operating in Class-B to solve hard start-up problem of the Class-C oscillator. Under the DC supply of 1.1 V, the circuit power consumption is 2.5 mW, the operation frequency is from 10 to 10.7 GHz, (i.e., 6.7% tuning range). The measured output power after adding cable loss is −5.3 ~ −8.2 dBm, and the best phase noise at the 1-MHz offset frequency is -108.6 dBc/Hz, and the best FOM and FOMT are -184.7 dBc/Hz and -181.4 dBc/Hz respectively. The chip area including I/O PAD is 0.89 × 0.69 mm2. III. An X-band integer-N Phase Locked Loop (PLL) with Class-F Voltage-Controlled Oscillator This circuit uses the first designed class-F voltage-controlled oscillator to implement an integer phase-locked loop (PLL) in X-band. The circuit includes a voltage-controlled oscillator, a current mode logic divider, a differential to single buffer, TSPC dividers, full-swing buffers, phase and frequency detector, a charge pump, and a loop filter. Chapters include an introduction and analysis of each sub-circuit. The measurements are listed as, the PLL is locked from 9.63 to 10.28 GHz when reference signal is 37.64 to 40.16 MHz. The division ratio is dual-mode 256 and 260. The overall power consumption is about 46.8 mW. The chip area including the I/O PAD is 1.2 × 0.95 mm2. At the center frequency of 10 GHz, the reference spur is as low as -45 dBc and phase noise is -96.9 dBc/Hz at 1-MHz offset. The clock jitter from 10 kHz to 40 MHz (SSA instrument measurement limit) is 940 fsec.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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