應用0.25 μm GaN/SiC HEMT於連續B類 X頻段功率放大器與K頻段 WIPD 覆晶功率放大器暨90奈米 CMOS FR3 寬頻發射器之研製;Design and Implementation of a 0.25 μm GaN/SiC HEMT Continuous Class-B X-Band Power Amplifier, K-Band WIPD Flip-Chip Power Amplifier, and 90-nm CMOS FR3 Wideband Transmitter

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/96325

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/96325

Title:	應用0.25 μm GaN/SiC HEMT於連續B類 X頻段功率放大器與K頻段 WIPD 覆晶功率放大器暨90奈米 CMOS FR3 寬頻發射器之研製;Design and Implementation of a 0.25 μm GaN/SiC HEMT Continuous Class-B X-Band Power Amplifier, K-Band WIPD Flip-Chip Power Amplifier, and 90-nm CMOS FR3 Wideband Transmitter
Authors:	陳柏豪;Chen, Po-Hao
Contributors:	電機工程學系
Keywords:	連續B類 X頻段功率放大器;K頻段 WIPD 覆晶功率放大器;FR3 寬頻發射器
Date:	2024-11-25
Issue Date:	2025-04-09 17:48:55 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文使用穩懋半導體公司(WINTM)所提供之 0.25 μm GaN-on-SiC HEMT 與 0.25μm GaN/SiC HEMT 和 GaAs IPD 覆晶技術與台灣積體電路製造股份有限公司 (tsmcTM ) 所提供之90-nm CMOS 1P6M製程，分別進行X頻段之氮化鎵連續B類模式功率放大器、K頻段功率放大器採用0.25μm GaN/SiC HEMT 和 GaAs IPD 覆晶技術以及FR3頻帶之寬頻發射機之設計。第一顆晶片提出使用WINTM 0.25 μm GaN-on-SiC HEMT製程設計於X頻段B類連續模式氮化鎵功率放大器，輸出匹配電路採用連續B類模式，針對基頻和二階諧波阻抗進行匹配，並且透過挑選偏壓，改善線性度，來達到寬頻且高效率的功率放大器。量測結果顯示最佳功率增益為 16.15 dB，3-dB 頻寬為 9.0 - 11.0 GHz，飽和輸出功率為 35.27 dBm，功率附加效率最高可達 24.12 %，1-dB 增益壓縮點輸出功率為21.06 dBm，晶片面積為 4.59 (2.70 × 1.70) mm2。第二顆晶片提出應用於K頻段功率放大器採用0.25 μm GaN/SiC HEMT 和 GaAs IPD 覆晶技術，在設計中透過覆晶技術，縮小化GaN 晶片尺寸，由於GaAs IPD 製程的成本約為 GaN 0.25 µm 製程的四分之一，所以可以藉此來降低總成本。在此次設計中所採用的過渡傳輸線中，應用頻率可以高達 51 GHz。量測結果顯示最佳輸出功率增益為11 dB ，3-dB 頻寬為24.5 - 27.8 GHz，飽和輸出功率為 25.16 dBm，功率附加效率最高可達 12.49 %，晶片面積為 3.32 (2.55 × 1.3) mm2。第三顆晶片提出應用於FR3頻帶之寬頻發射機，為單路同相(In-phase)之發射機，使用台灣積體電路製造股份有限公司 (tsmcTM) 90-nm CMOS 製程設計。在基頻部分使用CMOS基頻反向式放大器以及電阻回授以提升輸出阻抗，並簡化偏壓設計。升頻混頻器採用被動混頻器來達到低功耗以及高線性度的特性，功率放大器之驅動級使用疊接架構達到較高之轉換增益以提高輸出功率，以及使用電阻電容串聯回授改善穩定度。量測時固定本地震盪驅動訊號為10 dBm時，操作頻帶為9 - 12 GHz，量測到最大轉換增益為 9.35 dB，輸出1-dB 增益壓縮點功率為-1.79 dBm，輸出功耗為49.2 mW，晶片面積為0.9 mm2 (1.23 mm × 0.73 mm)。 ;This thesis presents the design and fabrication of various RF power amplifiers using different technologies, including WIN′s 0.25-µm GaN/SiC, GaAs Integrated Passive Device (IPD) technology, and tsmc′s 90-nm CMOS 1P6M process. The three designs include: 1). A continuous class-B mode power amplifier for X-band applications using GaN/SiC technology, 2). A flip-chip assembled K-band power amplifier (PA) and 3). A broadband transmitter for the FR3 band. The first chip is a continuous class-B mode power amplifier designed for the X band,utilizing GaN/SiC technology. Its output matching network is optimized for both fundamental and second harmonic frequencies to meet the requirements of continuous class-B mode operation. By fine-tuning the biasing, the linearity of the amplifier is improved. The design achieves a 3-dB bandwidth ranging from 9.0 to 11.0 GHz, with a small-signal gain of 16.15 dB. Continuous wave (CW) measurements show a maximum saturated output power of 35.27 dBm, a power-added efficiency (PAE) of up to 24.12%, and an OP1dB of 21.06 dBm. The chip size measures 4.59 mm² (2.7 mm × 1.7 mm). The second chip is a flip-chip assembled K-band PA, developed using WIN Semiconductors’ 0.25-µm GaN/SiC technology and GaAs IPD technology. Flip-chip technology reduces the overall cost by minimizing the GaN chip size, while GaAs IPD chips,costing about one-quarter of GaN 0.25 µm chips, further contribute to cost efficiency. This optimized transition can be applied to frequencies up to 51 GHz. The fabricated PA achieves a saturated output power of 25.16 dBm, a peak PAE of 12.49%, a gain of 11 dB, and a 3-dB bandwidth from 24.5 to 27.8 GHz. The chip size is 3.32 mm² (2.55 mm × 1.3 mm). This work demonstrates the feasibility of using flip-chip assembly technology for K-band PA design. The third chip is a broadband transmitter designed for the FR3 band. It is a single-channel in-phase transmitter fabricated using tsmc′s 90-nm CMOS technology. The design incorporates a CMOS baseband inverter-type amplifier with resistive feedback, which increases the output impedance in the baseband circuit. A passive mixer is used for up-conversion, chosen for its low power consumption and high linearity. The driver amplifier employs a cascode topology to enhance conversion gain, improving output power performance. To ensure stability, resistor-capacitor (RC) feedback is applied to the driver amplifier. The proposed I-channel transmitter achieves conversion gain of 9.35 dB, with an output 1-dB compression point (OP1dB) of -1.79 dBm under a local oscillator (LO) power of 10 dBm at a center frequency of 11 GHz. The measured gain bandwidth spans from 9 to 12 GHz. The chip consumes 49.2 mW of DC power and has a total area of 0.9 mm² (1.23 mm × 0.732 mm).
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	18	View/Open

社群 sharing

Loading...