微型化雙頻平衡式微波被動電路設計;Miniaturized Dual-Band Balanced Microwave Passive Circuit Design

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题名:	微型化雙頻平衡式微波被動電路設計;Miniaturized Dual-Band Balanced Microwave Passive Circuit Design
作者:	張威銍;Chang, Wei-Chih
贡献者:	電機工程學系
关键词:	雙頻;微型化;平衡式;毫米波;帶通濾波器;功率分配器;Dual-band;Miniaturized;balanced;Millimeter-wave;Bandpass Filter;Power divider
日期:	2024-12-03
上传时间:	2025-04-09 17:49:14 (UTC+8)
出版者:	國立中央大學
摘要:	本論文以微型化雙頻平衡式微波被動電路為研究目標，提出雙頻平衡式帶通濾波器以及功率分配器之設計，設計上使用雙頻橋式T線圈(Bridged-T Coil, BTC)取代傳輸線，同時達到電路尺寸微型化與雙頻操作的效果。首先，以WIPD製程實現18.7/38.5-GHz雙頻平衡式帶通濾波器，成功實現雙頻操作且具共模雜訊吸收效果，其電路面積為2.23 mm × 2.06 mm，在兩中心頻率之電氣尺寸分別為0.140 × 0.130與0.30 × 0.270。接著，分別以WIPD製程與TSMC 90-nm CMOS製程實現雙頻平衡式功率分配器，以WIPD製程實現之18.7/38.5-GHz雙頻平衡式功率分配器，其電路面積為2.38 mm × 1.9 mm，在兩中心頻率之電氣尺寸分別為0.150 × 0.120與0.30 × 0.240。而以TSMC 90-nm CMOS製程實現之10.7/20-GHz雙頻平衡式功率分配器，其電路面積為1.14 mm × 1.25 mm，在兩中心頻率之電氣尺寸分別為0.040 × 0.0440與0.080 × 0.0840。上述電路實測效能良好，相較於既有之相關設計，均成功達成大幅縮減電路面積之目的。 ;This thesis focuses on the design of miniaturized dual-band balanced microwave passive circuits, and the design of a dual-band balanced bandpass filter and a dual-band balanced power divider are proposed. By using the dual-band design of bridged-T coils, both circuit miniaturization and dual-band operation are achieved simultaneously. First, the proposed 18.7/38.5-GHz dual-band balanced band-pass filter is implemented using the WIPD process. The proposed design successfully achieves the desired dual-band frequency characteristic along with the absorption of common-mode noise. The circuit size is only 2.23 mm × 2.06 mm, while the corresponding electrical sizes are 0.14λ₀ × 0.13λ₀ at 18.7 GHz and 0.3λ₀ × 0.27λ₀ at 38.5 GHz. Next, two dual-band balanced power dividers are implemented using the WIPD and TSMC 90-nm CMOS processes. The proposed 18.7/38.5-GHz dual-band balanced power divider in WIPD features a circuit size of 2.38 mm × 1.9 mm. The corresponding electrical sizes are 0.15λ₀ × 0.12λ₀ at 18.7 GHz and 0.3λ₀ × 0.24λ₀ at 38.5 GHz. The proposed 10.7/20-GHz dual-band balanced power divider implemented with the TSMC 90-nm CMOS process features a very compact circuit size of only 1.14 mm × 1.25 mm. The corresponding electrical sizes are 0.04λ₀ × 0.044λ₀ at 10.7 GHz and 0.08λ₀ × 0.084λ₀ at 20 GHz. The measured performance of these circuits is good. Compared to existing designs, they successfully achieve significant circuit size reduction.
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