| 摘要: | 隨近年來資料傳輸速率不斷提升，且由於通道近似於低通濾波器的特性，使得資料經過通道後會受到嚴重的衰減，造成符碼間干擾(Inter Symbol Interference, ISI)以及訊號完整度的問題，進一步造成接收端無法將資料正確判斷，使得後方電路運作錯誤以及誤碼率的上升。等化器的作用就是補償資料受到傳輸通道造成的高頻衰減，確保資料能夠被正確的判斷出來。此外，為了使等化器能夠適用於不同的通道衰減，會將等化器中加入自適應機制，使其能根據不同的通道衰減，自動偵測並給予資料最佳化的補償量。
在自適應系統的應用上，傳統的作法會將雙端差動的資料透過差動訊號相減的方式來判斷資料的邏輯，但是當傳輸通道的衰減嚴重到一定的程度，即使資料經過連續時間線性等化器的初步補償，資料的邏輯仍無法被輕易的判斷。這會使得後方電路無法正常運作，或導致自適應系統操作異常而收斂至不正確的位置，給予資料錯誤的補償量。因此本論文提出了一個應用於高通道衰減之自適應等化器，可以靈活運用在-11.40 dB至-31.91 dB衰減的通道，並且提出一個組合式資料型樣偵測器(Combinational Data Pattern Detector, CB-DPD)，使得資料就算受到嚴重的衰減也能夠將正確的資料型樣判斷出來，並且提供給自適應逼零演算法(Zero-forcing Algorithm)使用，使資料獲得最佳化的補償。
本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程實現，電路操作電壓為1V，輸入資料為8 Gb/s NRZ訊號，並且利用PRBS-7進行編碼，輸入時脈的速率為4 GHz，等化器可以補償之通道衰減的範圍為-11.40 dB至-31.91 dB，並且於短通道的佈局後模擬中眼高為406.86 mV，眼寬為110.92 ps；長通道的佈局後模擬中眼高為120.61 mV，眼寬為79.38 ps。此外，本論文所提出的CB-DPD比起傳統一般的DPD，輸出的眼高增加了58.74%。整體的功率消耗為21.70 mW，其中等化器的部分為9.02 mW，佔了41.57%；自適應的部分則為12.68 mW，佔了58.43%，晶片面積為1.13 mm²，其中核心電路面積為0.079 mm²。
;In recent years, as data transmission rates have continuously increased, the channel′s low-pass filter characteristics have caused significant signal attenuation after transmission. This leads to inter-symbol interference (ISI) and signal integrity issues, making it difficult for the receiver to correctly interpret the data. As a result, downstream circuits may malfunction, and the bit error rate (BER) may increase. The role of an equalizer is to compensate for high-frequency attenuation caused by the transmission channel, ensuring the data can be accurately interpreted. Additionally, to adapt the equalizer to various levels of channel attenuation, an adaptive mechanism is incorporated, allowing it to automatically detect and provide optimal compensation based on the channel′s attenuation characteristics.
In traditional adaptive systems, differential data signals are typically compared to determine their logic states. However, when the transmission channel experiences severe attenuation, even after initial compensation by a continuous-time linear equalizer (CTLE), the data logic may remain difficult to discern. This can cause downstream circuits to malfunction or the adaptive system to converge to an incorrect state, leading to improper compensation.
This study proposes an adaptive equalizer for high loss channels, capable of handling attenuation ranging from -11.40 dB to -31.91 dB. It also introduces a Combinational Data Pattern Detector (CB-DPD), which can accurately identify data patterns for zero-forcing algorithm even under severe attenuation and provide the optimal compensation for the data.
The proposed design is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operates at 1V, inupt 8 Gbps NRZ data signals encoded with PRBS7, and uses a 4 GHz clock. The equalizer compensates for channel attenuation within a range of -11.40 dB to -31.91 dB. Post-layout simulation results show an eye height of 406.86 mV and an eye width of 110.92 ps for short channels, while for long channels, the eye height is 120.61 mV and the eye width is 79.38 ps. Furthermore, the proposed CB-DPD increases the output eye height by 58.74% compared to conventional DPD.The total power consumption is 21.70 mW, with the equalizer consuming 9.02 mW (41.57%) and the adaptive system consuming 12.68 mW (58.43%). The chip area is 1.13 mm², with a core circuit area of 0.079 mm². |
