新型單電晶體多鐵電穿隧接面非揮發式記憶體矩陣之研製與特性分析;Fabrication and Characterization of Novel 1 Transistor-n-Ferroelectric-tunnel-junction (FTJ) Non-volatile Memory

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Title:	新型單電晶體多鐵電穿隧接面非揮發式記憶體矩陣之研製與特性分析;Fabrication and Characterization of Novel 1 Transistor-n-Ferroelectric-tunnel-junction (FTJ) Non-volatile Memory
Authors:	陳之遠;Chen, Chih-Yuan
Contributors:	電機工程學系
Keywords:	非揮發性記憶體;鐵電穿隧接面記憶體;記憶體矩陣;電壓讀取;隨機電報雜訊;Non-Volatile Memory(NVM);Ferroelectric Tunnel Junction(FTJ);memory array;Voltage readout;Random Telegraph Noise(RTN)
Date:	2025-01-17
Issue Date:	2025-04-09 17:50:26 (UTC+8)
Publisher:	國立中央大學
Abstract:	在科技快速發展的時代中，隨著記憶體尺寸微縮，傳統記憶體受限於物理的極限而無法繼續發展，於是各式新興記憶體(emerging memory)被發明，其中包含以 HfO2/ZrO2 (HZO)作為鐵電材料層的鐵電記憶體(Ferroelectric memory)，相較於傳統鈦酸鋇(BaTiO3 , BTO)和鋯鈦酸鉛(Pb[ZrxTi1-x]O3 , PZT)材料的鐵電記憶體，HZO材料具有更好的微縮潛力以及能與互補式金屬氧化物半導體(Complementary Metal-Oxide Semiconductor, CMOS)做整合，所以本篇論文將以鐵電穿隧接面記憶體(Ferroelectric Tunnel Junction, FTJ)為基礎設計一個 1T16FTJ作為 unit cell，並實現記憶體矩陣的操作，實驗的內容包含光罩佈局、製程以及量測，製程實驗在台灣半導體研究中心(Taiwan Semiconductor Research Institute, TSRI)完成。鐵電記憶體是由金屬-鐵電層-金屬(Metal-Ferroelectric-Metal, MFM)所組成，本次實驗是將16個FTJ cells的下電極連接到一個控制電晶體的汲極(Drain)端，將上電極連接到獨立的位元線(Bit line, BL)，下電極則是與控制電晶體drain端一起連接到數據線(Data line, DL)，進行資料的寫入(PROGRAM)、抹除(ERASE)以及讀取(Read)，控制電晶體的閘極端(gate)連接到字元線(Word line, WL)，源極端(Source)則是連接到來源線(Source line, SL)。在讀取資料方面，由於讀取電流的方式會產生電流較小或是儲存狀態差異不明顯，導致資料誤判的情況發生，故本篇論文將展示以電壓讀取取代傳統讀取電流的方式，電壓讀取具有較大的記憶窗口(memory window, MW)，在耐久度測試(Endurance) 以及資料保存時間(Retention)方面會表現較好，在量測過程中發現了隨機電報雜訊 (Random Telegraph Noise, RTN)現象導致 MW下降的情況，透過量測與計算出其缺陷的深度與能量，並發現其缺陷位置位於鐵電介電層與電極的接面附近。;In the era of rapidly developing technology, as memory size keeps scaling down, several conventional memory technologies have faced their physical limits. Thus, the invention of emerging memories leads to the replacement of conventional memory. These emerging memories include ferroelectric memories, which are composed of HfO2 and ZrO2. Compared to barium titanate(BaTiO3 , BTO) and zirconium titanate(Pb[ZrxTi1-x]O3 , PZT), HZO materials offer better scalability and have also been integrated into complementary-metal-oxide semiconductor (CMOS) processes. This work proposes a 1-transistor-and-16-ferroelectric tunneling-junction (1T16FTJ) design as a unit cell, and applies 1T16FTJ in memory arrays. The experiment included mask layout, fabrication and measurement, the samples were fabricated at Taiwan Semiconductor Research Institute(TSRI). Ferroelectric memory is composed of Metal-Ferroelectric-Metal(MFM) layers. In this work, we connected 16 FTJ cells to the drain of the transistor, each FTJ cell has an individual BL linked to its top electrode, and the bottom electrode is connected to a shared DL at the drain of the transistor in order to PROGRAM, ERASE and read. The gate of the transistor is connected to WL and the source is connected to SL. The 1T16FTJ memory has faced challenges such as low read current and insufficient current differentiation between storage states, leading to data misjudgment. This work will utilize voltage readout to replace the conventional current readout, because voltage readout has a larger MW, better retention and endurance performance. During the measurement, the phenomenon of RTN was discovered, which leads to the narrowing of the MW. By measuring and calculating, we identified the depth and energy of RTN traps, and found that the RTN traps are located near the interface between the top electrode and the HZO layer.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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