利用三維串列對稱網格模擬P-N球接面之崩潰現象

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姓名

陳伯騏(Po-chi Chen) 查詢紙本館藏

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電機工程學系在職專班

論文名稱

利用三維串列對稱網格模擬P-N球接面之崩潰現象
(Breakdown Simulation of a Spherical P-N Junction with a String of 3D Symmetrical Grids)

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摘要(中)

本論文主要研究方向為開發串列對稱網格，探討其架構規則性，並加入離子撞擊游離模型於三維模擬器內，用以模擬半導體元件內部載子雪崩崩潰之物理現象。在理論基礎方面，我們運用波松方程式、電子流連續方程式與電洞流連續方程式，模擬三維半導體元件中載子漂移、產生與複合之特性。模擬架構方面，先研究串列網格之規則性，再藉由網格對稱性的原則，推導出模擬元件所需之各項物理參數。
　　最後我們應用此開發模擬模型，分析比較在不同擴散半徑與相異參雜濃度下其崩潰電壓的改變狀態，與其相對應關係為何，並與三維直角座標之撞擊游離模型進行比較，進而驗證本研究所開發之串列對稱網格模型不但具備模擬結果相同之準確性，更有效縮短崩潰模擬的時間為原本的四萬分之一，大幅提昇元件設計的便利性。

摘要(英)

The paper aims to develop a string of 3D symmetrical grids to simulate the breakdown of a spherical P-N junction. Firstly, the regularity of 3D symmetrical grid is discussed. Secondly, with the purpose of finding the result of avalanche breakdown in P-N junction, the impact-ionization model is added into the 3D model. The Poisson equation and the equations of continuity for electron and hole are formulated into a subcircuit format, which are suitable for general circuit simulator in the equivalent circuit approach. The rule of embedding the symmetrical grids into the subcircuit format is analyzed to get the required parameters. Thirdly, the proposed model was applied to compare its breakdown voltage on different junction radius and different doping concentration to get the relationship on these parameters. Lastly, compared to the model in 3D rectangular coordinates, the 3D symmetrical grid is highly accurate and very fast for the breakdown simulation of a spherical PN junction.

關鍵字(中)

★ P-N球接面
★ 串列網格
★ 崩潰模擬

關鍵字(英)

★ breakdown simulation
★ spherical P-N junction
★ string of 3D symmetrical grids

論文目次

中文摘要..................................................i
英文摘要.................................................ii
誌謝....................................................iii
目錄.....................................................iv
圖目錄....................................................v
表目錄.................................................viii
第一章簡介...............................................1
第二章 PN二極體元件三維模擬架構與探討.....................3
　　2-1. 三維等效電路架構.................................3
　　2-2. 直角座標之三維等效電路元件模擬探討...............6
　　2-3. 球座標之任意角度三維等效電路元件模擬探討.........8
　　2-4. 球座標之軸對稱三維等效電路元件模擬探討..........11
第三章三維串列對稱網格元件結構解析......................12
　　3-1. 串列對稱網格結構定義............................12
　　3-2. 串列對稱網格結構推導............................15
　　3-3. 串列對稱網格元件結構下之模擬參數計算............23
第四章三維串列對稱網格元件崩潰特性模擬分析..............34
　　4-1. 三維串列對稱網格元件崩潰特性模擬................34
　　4-2. 不同擴散半徑之崩潰電壓比較......................38
　　4-3. 不同濃度之崩潰電壓比較..........................41
　　4-4. 不同銳角之崩潰電壓比較..........................43
第五章結論..............................................45
參考文獻.................................................46

參考文獻

[1] C. C. Huang. “Semiconductor Devices with 16nm Technology”, NARL Quarterly, 28, pp. 86-91, Oct. 2010.
[2] C.H. Pai, “Development of 3D Impact-Ionization Model and its Applications to Breakdown Simulation of Spherical P-N Junction”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, July. 2011.
[3] C. C. Chang, “Verification of 1D BJT Numerical Simulation and its Application to Mixed Level Device and Circuit Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2001.
[4] R. N. Chang, “Parameter Extraction of Impact Ionization Rate in Two-Dimensional PIN Diode Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2011.
[5] C. C. Chang, C. H. Huang, J. F. Dai, S. J. Li, and Y. T. Tsai, “3-D Numerical Device Simulation Including Equivalent-Circuit Model”, IEDMS, 2002.
[6] P. C. H. Chan and C. T. Sah, “Exact Equivalent Circuit Model for Steady-state Characterization of Semiconductor Devices with Multiple-Energy-Level Recombination Centers”, IEEE Transactions Electron Devices, vol. ED-26, no. 6, pp. 924-936, 1979.
[7] C. L. Teng, “An Equivalent Circuit Approach to Mixed-Level Device and Circuit Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[8] Z. C. Liu, “Comparison of Two Potential Variables in Mixed-Level Device and Circuit Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1998.
[9] C. C. Chang, J. F. Dai, and Y. T. Tsai, “Verification of 1D BJT Numerical Simulation and its Application to Mixed-Level Device and Circuit Simulation”, Int. J. of Numerical Modelling: Electronic Networks. Devices and Fields, pp. 81-94, 2003.
[10] S. J. Li, “An Equivalent Circuit of Impact-Ionization and its Applications on Semiconductor Devices”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2002
[11] Ben G. Streetman and Sanjay Banerjee, “Solid State Electronic Devices”, Prentice Hall, 2000.
[12] Dr. Simon M. Sze, “Semiconductor Devices: Physics and Technology, 2nd Ed.”, 564 pages, Wiley, New York, 2002.
[13] Y. S. Tso, “Analysis and Simulation Cylindrical Coordinates of Curved P-N Junction Properties”, M. S. Thesis, Institute of EE, Nation Central University, Taiwan, Republic of China, Jun. 2002.
[14] P. S. Chang, “Development of 2D Template Device Simulator Including Impact Ionization Models”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, June. 2006.
[15] M. S. Li, “Rectangular Transform of Trapezoidal Mesh and Its Application to Cylindrical MOSFETs”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, June. 2011.
[16] C. H. Lee, “A Small-Angle Method for Breakdown Simulation in 2D Circular P-N Junction”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, June. 2011.
[17] Dr. Simon M. Sze, “Semiconductor Devices: Physics and Technology, 2nd Ed.”, 564 pages, Wiley, New York, 2002.
[18] J. Z. Wang, “Curvature Effect and Back Gate Bias Effect on Semiconductor Device Breakdown Simulation”, M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, June. 2009.

指導教授

蔡曜聰(Yao-tsung Tsai)

審核日期

2012-7-10

推文