本論文中，主要目的是想利用固相結晶法在550 oC環境中進行回火24小時，達到增加元件主動層中晶粒尺寸，減少晶界數目，提升含鍺量子點薄膜電晶體的光增益，改善載子在通道的傳輸速率及操作電流。從本實驗室之前所開發的鍺量子點薄膜電晶體的量測結果中，發現無鍺量子點薄膜電晶體，其照光下汲極飽和電流與未照光時汲極飽和電流相比具有35%的增益，而上部閘氧化層耦合鍺量子點薄膜電晶體可達65%的增益。雖然光響應的確可經由鍺量子點較佳的吸光率而增強，但是增加幅度不如預期。我們推測是因為複晶矽通道中為數眾多的晶界受到照光時也會激發出電子/電洞對，因而對無鍺量子點薄膜電晶體的光增益有所貢獻。並且由於通道中晶界對於載子而言屬於一種缺陷，而造成照光下鍺量子點激發出的主要載子進入通道後的載子遷移率較低，使得光響應較不那麼明顯。因此本論文利用非晶矽固相結晶法 (solid phase crystallization，SPC) 形成元件主動層，再以LPCVD系統所沉積而成的複晶矽薄膜做為一對照組，藉此分析n型與p型元件光響應的差別。 The main purpose of this thesis is to investigate how to improve the photoresponse of poly-Si TFTs with Ge QDs using SPC of a-Si in channel fabrication. We have successfully demonstrated that the photoresponse of poly-Si TFTs could be enhanced by a factor of 2 by incorporating Ge QDs into the gate oxide. However we know that a polycrystalline silicon film deposited by LPCVD system (as-deposited poly-Si) at 620 oC has smaller grains and more grain boundaries. Grain boundaries in the channel behave like traps to reduce the carrier mobility, and carrier lifetime. Consequently, active carriers excited from Ge QDs under illumination injected into channel are more likely recombined by the trap, leading to a less photocurrent enhancement. In this thesis, we employ a crystallization method, solid-phase-crystallization of amorphous silicon (SPC of a-Si) annealing at 550 oC for 24 hours, to increase the grain size and reduce the numbers of grain boundaries to increase the photocurrent in TFTs incorporating Ge QDs in the top-gate dielectric.
