本篇論文提出可適用於IEEE 802.16e標準的多碼率LDPC解碼器，目前LDPC解碼器在序列化的架構上，記憶體的使用率是很高的，在減少面積與硬體複雜度的前提下，記憶體所佔有的比重也會越來越大。同時為了使速度達到最佳化，用管線技術增加硬體使用率，記憶體必須具備同時讀寫的能力，因此採用雙埠記憶體的LDPC解碼器是普遍的。本篇論文特別針對此記憶體做優化與改良，採用單埠記憶體來取代雙埠記憶體，單埠記憶體比起雙埠記憶體在功率與面積上都佔有優勢，如何在相同記憶容量與不增加速度的前提下，將雙埠記憶體取代是本論文的重點。單埠的缺點在於不能同時間讀寫，因此在資料存取的排序上必須特別規劃，本論文針對IEEE 802.16e標準其六種檢查矩陣特別設計對應的資料排程以及資料在記憶體的位置，同時將記憶區塊拉出檢查節點與位元節點形成共用的第三區塊。經由FPGA驗證得知，單埠記憶體可完全取代雙埠記憶體以節省面積與功率，但在速度上會隨著檢查矩陣碼率的提高，而略劣於雙埠記憶體。由ISE軟體合成電路後可知本論文LDPC所提出之架構可以有最高112.94Mbps的生產量。 This thesis proposes a multi-code rate LDPC decoder in the application of IEEE 802.16e. The utilization rate of memory is very high when the LDPC decoder uses a serial architecture. To reduce the complexity of hardware, the percentage of memory unit is getting higher. In order to optimize the throughput rate, pipline technique can increase the hardware utilization. However, such architecture needs the memory to read and write at the same time. Hence the LDPC decoder usually uses two-port memory. This thesis focuses on the optimization and modification of memory design. We use single-port memory to replace two-port memory because single-port memory has the advantage of power consumption and area. The weakness of single-port memory is it cannot read and write at the same time. We should carefully arrange the data access schedule. In this thesis, we have designed the memory access schedules according to six parity check matrices for IEEE 802.16e. In the FPGA emulation results, single-port memory can completely replace the two port memory to save the chip area and power consumption. The throughput rate would be lower than two-port memory architecture as the code rate increases. Finally, the throughput rate of the proposed LDPC decoder can achieve 112.94 Mbps.
