English  |  正體中文  |  简体中文  |  Items with full text/Total items : 66984/66984 (100%)
Visitors : 23164814      Online Users : 452
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/31828


    Title: Effective Decap Insertion in Area-Array SoC Floorplan Design
    Authors: Lu,Chao-Hung;Chen,Hung-Ming;Liu,Chien-Nan Jimmy
    Contributors: 電機工程研究所
    Date: 2008
    Issue Date: 2010-07-06 18:12:26 (UTC+8)
    Publisher: 中央大學
    Abstract: As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common approach t
    Relation: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS??
    Appears in Collections:[電機工程研究所] 期刊論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML281View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback  - 隱私權政策聲明