Efficient block-level connectivity verification algorithms for embedded memories

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/32392

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/32392

Title:	Efficient block-level connectivity verification algorithms for embedded memories
Authors:	Li,JF
Contributors:	電機工程研究所
Keywords:	FAULT MODEL;CIRCUITS
Date:	2004
Issue Date:	2010-07-06 18:26:14 (UTC+8)
Publisher:	中央大學
Abstract:	A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if mult
Relation:	IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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