Built-in redundancy analysis for memory yield improvement

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/32466

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/32466

Title:	Built-in redundancy analysis for memory yield improvement
Authors:	Huang,CT;Wu,CF;Li,JF;Wu,CW
Contributors:	電機工程研究所
Keywords:	RANDOM-ACCESS MEMORY;EMBEDDED RAMS;REPAIR;DRAM;BIST
Date:	2003
Issue Date:	2010-07-06 18:28:48 (UTC+8)
Publisher:	中央大學
Abstract:	With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the
Relation:	IEEE TRANSACTIONS ON RELIABILITY
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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