| 摘要: | 隨著世界的進步與發展導致大量自然資源的使用及能源的需求，使得能源快速消耗，更因為自然資源的有限，因此如何有效利用能源、節省不必要的能源開支成為日後相當重要的問題。 功率金氧半場效應電晶體被大量應用在許多方面，包括消費性電子產品、電腦、通訊、汽車電子及家電，由於節能意識的抬頭，如何降低元件的功率損耗成為元件設計者的目標。對低壓功率金氧半電晶體，提出羽翼狀晶胞設計其結合了方型及線型晶胞。羽翼狀晶胞移除部份晶胞間的複晶矽面積，因此增加了通道密度及電流路徑，導通電阻值可因此降低。羽翼狀晶胞的設計可被應用在平面式閘極及溝槽式閘極的功率金氧半場效應電晶體。 對高壓功率金氧半電晶體，由於寄生接面場效應電晶體電阻，長閘極是不可避免的，因而造成元件的低切換速度及高切換損耗。針對此問題提出結合分離式閘極及浮接np型井區，與使用全面性離子佈植的功率金氧半場效電晶體的設計來改善元件的切換問題。分離式閘極移除部份的閘極面積來達到提高切換速度的目的，而np型井區則避免了電場的聚集。全面性離子佈植則藉由提高表面的濃度，使閘極縮短時能抑制寄生電阻的增加。With the progress and development of the world, it results in a great mount of natural resources use and the energy requirement and rapid consumption of the energy. Due to the limited natural resources, how to use the energy efficiently without wasting becomes an important question. Power metal oxide semiconductor field effect transistor are used widely in a lot of fields includes consumer electronics, computers, communication, car electronics, and home appliances. Due to the energy saving, how to reduce the power loss becomes a target for devices designers. For low voltage power VDMOSFETs, it proposed wing cell design, combining the square cell and linear cell. The wing cell removes a part of the poly area between each cell. Therefore, both the channel density and current path can be increased. Consequently, the on-resistance can be reduced efficiently. The wing cell design can be used to the planar-gate and trench-gate power VDMOSFETs. For high voltage power VDMOSFETs, the long gate length can not be avoided because the parasitic JFET resistance. Due to this reason, low switching speed and high switching loss occur. In order to decrease them, a split gate with floating np-well power VDMOSFET and overall implant power VDMOSFET are proposed. The split gate with floating np-well power VDMOSFET removes a part of gate area. However, the electric field crowding and high on-resistance were happened at the same time. Consequently, a floating np-well is incorporated to solve it. On the other hand, shortening the gate length is a more easy way to improve switching speed and switching loss. But, the parasitic JFET resistance increases rapidly with the shortened gate length. Therefore, a high concentration layer is required to restrain the parasitic JFET resistance while shortening the gate length. |
