本論文在設計上分為兩部份，第一部份是以CMOS製程實現全積體化功率放大器為目標，使用功率結合變壓器技術達到大功率輸出之功率放大器。第二部份則以設計兩個寬頻E類功率放大器為目標，第一個電路為以CMOS製程實現應用電抗補償網路與負電容補償之寬頻E類功率放大器，第二個電路是以pHEMT製程實現應用雙諧振電抗補償網路之寬頻E類功率放大器。 各電路特性量測如下：第一部份以CMOS製程實現功率結合變壓器技術之功率放大器的電路，增益量測為14.3 dB，1-dB增益壓縮點輸出功率為20.2 dBm，飽和輸出功率為25.3 dBm，功率增進效率為24.2 %。而在第二部份，第一個是以CMOS製程實現應用電抗補償網路與負電容補償之寬頻E類功率放大器的電路，經量測結果顯示在1.6 - 3.4 GHz範圍內由小到高為，功率增益為8.9 - 12.5 dB，功率增進效率為14.4 - 33.7 %，1-dB增益壓縮點輸出功率為14.8 - 18.3 dBm，飽和輸出功率為18.4 - 22.5 dBm；第二個是以pHEMT製程實現應用雙諧振電抗補償網路之寬頻E類功率放大器的電路，量測結果顯示在4.5 - 6 GHz範圍內由小到高的結果為，功率增益為9.7 - 13.3 dB，功率增進效率為37.2 - 50.8 %，1-dB增益壓縮點輸出功率為17 - 19.1 dBm，飽和輸出功率為18.5 - 20.8 dBm。 This thesis studies two categories of power amplifiers which are fully integrated silicon-based power amplifiers using power-combing transformer technique and broadband Class-E power amplifiers. Two Class-E amplifiers were studied in this thesis. The first CMOS broadband Class-E power amplifier was designed by using a negative capacitance to compensate the reactance at the output. The second pHEMT broadband Class-E power amplifier was fulfilled by using dual resonant reactance compensation technique. The measured results are summarized as follow, the CMOS power amplifier using power-combing transformer technique achieves a power gain of 14.3 dB, an output power at 1-dB gain compression point (P1dB) of 20.2 dBm, a saturation output power (Psat) of 25.3 dBm and a power-added efficiency (PAE) of 24.2 %. The CMOS broadband Class-E power amplifier using negative capacitance compensation technique achieves a bandwidth of 1.6 - 3.4 GHz, a power gain of 8.9 to 12.5 dB, a P1dB of 14.8 to 18.3 dBm, a Psat of 18.4 to 22.5 dBm and a PAE of 14.4 to 33.7 %. The pHEMT broadband Class-E power amplifier achieves a bandwidth of 4.5 - 6 GHz, a power gain of 9.7 to 13.3 dB, a P1dB of 17 to 19.1 dBm, a Psat of 18.5 to 20.8 dBm and a PAE of 37.2 to 50.8 %.
