應用傳輸線變壓器與功率結合技術於全積體化功率放大器之研究; The Study on Transmission Line Transformer and Power-Combining Techniques for Fully Integrated Power Amplifier Design

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/48505

Title:	應用傳輸線變壓器與功率結合技術於全積體化功率放大器之研究;The Study on Transmission Line Transformer and Power-Combining Techniques for Fully Integrated Power Amplifier Design
Authors:	黃亭堯;Ting-Yao Huang
Contributors:	電機工程研究所
Keywords:	功率放大器;變壓器;功率結合;power combining;transformers;power amplifier
Date:	2011-07-27
Issue Date:	2012-01-05 14:56:38 (UTC+8)
Abstract:	本論文架構以實現不同的功率結合器，並達到高傳輸效率，與阻抗轉換為目標，共分為兩大部分: 功率結合變壓器與傳輸線形態功率結合變壓器。第一部分分別設計兩個功率放大器搭配功率結合變壓器: “利用並聯功率結合變壓器之 CMOS 功率放大器”與“差動功率結合變壓器之E 類功率放大器”，並實現在 tsmcTM 0.18 μm CMOS 製程上，應用於2.4 GHz 頻段。第一設計為利用兩組AB 類差動對，搭配並聯型態的變壓器來結合四組放大器的輸出功率；第二設計為利用一對E 類差動放大器，搭配變壓器來結合兩組放大器的輸出功率。第二部分為利用傳輸線型態變壓器做功率結合，設計“應用傳輸線變壓器功率結合技術之 K 頻帶功率放大器”，採用AB 類功率放大器實現於WINTM 0.15 μm pHEMT 製程上，應用於K 頻帶。設計結果量測如下: 利用並聯功率結合變壓器之功率放大器，增益為19.8 dB，輸入反射損失約為10.2 dB，輸出反射損失為5.3 dB，1-dB 功率增益壓縮點輸出功率約為20.9 dBm，飽和輸出功率為26.7 dBm，最高功率增進效益為24.8 %，晶片面積為1.4 × 1.37 mm2 ；差動功率結合變壓器之E 類功率放大器，增益為12.98 dB， 1-dB 功率增益壓縮點輸出功率為23.3 dBm，飽和輸出功率約為 25.9 dBm，最高功率增進效益為29.9 %，晶片面積為1.33 × 1.11 mm2 ；應用傳輸線變壓器功率結合技術之K 頻帶功率放大器增益為10.2 dB，輸入反射損失約為 18.7 dB，輸出反射損失為11.48 dB，1-dB 功率增益壓縮點輸出功率約為22 dBm，此時的功率增進效益為23.4 %，晶片面積為1.5 × 1 mm2 。 The study of this thesis is to design different power combiners for power amplifier application, which can be used to achieve the high transmission efficiency and impedance transformation. The content of this thesis is divided into two parts. They are transformer and transmission line transformer (TLT) for power combining respectively. In the first part, we have designed two power amplifiers with power combining transformers. They are “A Parallel Power Combining Transformer for CMOS Power Amplifier” and “Differential Class E Power Amplifier Using Power Combining Transformer” respectively. The amplifiers were designed and implemented in tsmcTM 0.18 μm CMOS process for 2.4 GHz application. The first design is used of two class AB differential pairs, which were combined the output power from four groups of amplifiers by parallel power combining transformer. And the second design is used a class E differential pair, which were combined the output power from the two class E amplifiers by the power combining transformer. The second part of the thesis is related to the use of TLT for power combining in power amplifier design. A K-band class AB differential power amplifier with TLT was implemented in WINTM 0.15 μm pHEMT process. The measured results of these designs are summarized as follow. The CMOS power amplifier with parallel power combining transformer achieves a power gain of 19.8 dB, and input and output return losses are 10.2 dB and 5.3 dB respectively. The output 1-dB gain compression point (P1dB) is 20.9 dBm, and the saturated output III power is 26.7 dBm with the maximum power added efficiency of 24.8%. The chip size is 1.4 × 1.37 mm2. The differential class E power amplifier with power combining transformer achieves apower gain of 12.98 dB. The output 1-dB gain compression point (P1dB) is 23.3 dBm, and the saturated output power is 25.9 dBm, with the maximum power added efficiency of 29.9%. The chip size is 1.33 × 1.11 mm2. The K-band Power Amplifier with TLT power combining network achieves a power gain of 10.2 dB, and input and output return losses are 18.7 dB and 11.48 dB respectively. The output 1-dB gain compression point (P1dB) is 22 dBm with the power added efficiency of 23.4%. The chip size is 1.5 × 1 mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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