隨著三維晶片(3D IC)裡的矽穿孔(TSV)密度增加，兩訊號間互相干擾將會造成訊號傳輸品質發生問題。矽穿孔(TSV)串音干擾主要的因素取決於矽穿孔(TSV)的尺寸及矽穿孔(TSV)之間的間距(Spacing)。此外，矽基板(Slicon Substrate)的厚度及參雜濃度也發揮了重要的作用，它們影響基板接地的有效性。 本論文主要提出等效垂直十字鏈基板結構(Vertical-Cross-Chain Substrate Structure ; VCCSS)分析平台，針對矽穿孔(TSV)之間的耦合效應及使用屏蔽技巧(Shielding Technique)來加強模擬，並且在不同條件下做分析其包括矽基板浮接(Substrate Floating)、矽基板接地(Substrate Grounding)、保護環(Guard Ring)及接地矽穿孔(TSV Ground)。展現出從矽穿孔(TSV)底部到頂部基板接地會有一收集發散電流的深度效應。從串音干擾預防的觀點來看，無論是矽基板接地(Substrate Grounding)或是接地矽穿孔(Ground TSV)的方式皆比使用間距(Spacing)來的有效。 As for the Through-Silicon-Via (TSV) density increasing in the three-dimensional chip integration, the quality of signal transmission may be a problem on the signal interfering. The major factors of TSV crosstalk are determined by the size of TSVs and their spacing between two TSVs. In addition, the thickness of silicon dioxide and the doping concentration of the silicon substrate also play a key role, where they determine the total energy injecting into the substrate and the effectiveness of substrate grounding, respectively. In this thesis, a noise analysis platform for an advanced TSV model, called Vertical-Cross-Chain Substrate Structure (VCCSS), is proposed to discuss with the coupling and guarding effects including substrate floating, substrate grounding, p+ guard-ring and TSV ground on the TSV coupling. Besides of the effects for each situation, especially for substrate vertical effect, it is also shown the quantitative measure and better ways to prevent the interaction between signals.