由於近年來製程演進，使得快速傳輸大量資料已成為傳輸系統的主要動機，因此傳統的平行匯流排已不敷使用，取而代之的為目前被廣泛使用的高速串列傳輸系統。 本論文採用雙迴路架構，利用半速率取樣方式應用於3 Gbps的串列傳輸系統，此架構相似於超取樣式的概念，採用資料延遲視窗及取樣式相位偵測器取代傳統的D型正反器式的延遲單元。此方法可以只用一筆時脈對延遲後的資料做取樣而非使用多個時脈相位，可以避免走線的不匹配及降低設計困難度。雙迴路相位選擇式架構分別由多相位時脈倍頻器與資料回復電路所組成，其主要優勢在於二個獨立迴路，可以解決單一迴路中抖動轉移函數與抖動容忍度的頻寬互相衝突的問題，此外，利用鎖相迴路中震盪器的控制訊號控制延遲單元可以使延遲時間不受到製程電壓溫度變異的影響。若當輸入資料頻率發生抖動，頻率偵測器可以偵測出頻率差異並進行粗調調整相位繼續追鎖。 本論文之雙迴路架構採用TSMC 0.18 μm 1P6M CMOS製程，供應電源為1.8 V，輸入資料為3Gbps，取樣速率為1.5 GHz，經模擬驗證輸出回復時脈抖動為14.7 ps，並列輸出的回復資料抖動均小於15.8ps，晶片面積為1.13 mm2 。 In recent year, owing to the development of network and processor, the requirement of the high-speed data transmission has become the main motivation of transmission system. The conventional parallel bus shows the serious restriction while operating in the gigahertz range. As a result, the high-speed serial link technology is widely used so far for today’s data transmission system. This thesis presents a half-rate and dual-looped clock and data recovery (CDR) for the 3-Gbps data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only one clock instead of the multi-phase clock, and the complexity of the clock distribution network could be mitigated than counterpart. In addition, the control- mirroring signal stemming from the PLL locking signal indicates the robust of data delay segment of DDW in the process, voltage, and temperature variations. In terms of the bandwidth setting, both the DR and PLL bandwidth optimization for jitter suppression and the shortened acquisition time could also come to compromise. Besides, once the input data has frequency deviation, the use of the frequency detector would detect such data frequency difference and coarsely adjust the tracking phase in success. This thesis implements the dual-looped CDR circuit in TSMC 180 nm 1P6M CMOS process. Operating at the 3-Gbps data rate and 1.5-GHz clock frequency, the estimated peak to peak jitter of the recovered clock is 14.7 ps, and the recovered data jitter is less than 15.8 ps. The core area of CDR occupies 1.13 mm2.
