全數位快速鎖定四相位同步複製延遲電路;An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/54553

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題名:	全數位快速鎖定四相位同步複製延遲電路;An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit
作者:	葉蔭平;Yeh,Yin-ping
貢獻者:	電機工程研究所
關鍵詞:	全數位;四相位;快速鎖定;fast locked;all digital;four-phase
日期:	2012-07-24
上傳時間:	2012-09-11 18:53:57 (UTC+8)
出版者:	國立中央大學
摘要:	在系統晶片中，隨著速度越來越快，頻率不斷的提升，訊號同步電路扮演著關鍵性的角色，鎖相迴路和延遲鎖定迴路被廣泛地使用在晶片設計裡，但是，此兩種電路在特性上具有幾個問題，第一，由於上述兩種電路屬於閉迴路系統，產生頻寬方面的問題，需要考慮電路穩定性的問題。第二，電路花費較長的時脈週期才能完成輸入訊號以及輸出訊號的相位鎖定，在鎖定過程中需要較大的功率消耗，於是，同步複製延遲電路被設計出來，藉此改善上述的問題。傳統的同步複製延遲電路仍然有一些缺點，電路的相位誤差會受到輸出負載改變的影響而加大。另外，電路不具有多相位輸出，而且單位元件延遲時間太大導致電路的解析度不足。本論文提出一個具有四相位快速鎖定之時脈同步複製延遲電路，不僅擁有同步複製延遲電路的優點：快速鎖定與好的穩定性，並且擁有四相位的輸出訊號以及較高的解析度。本電路是以TSMC 90 nm 1P9M CMOS製程實現晶片，供應電壓為1.2 V，本電路的操作在頻率是在690 MHz ~ 1.38 GHz。在頻率1.38 GHz時的功率消耗為30mW。整體晶片面積為542 × 583 um2，內部核心電路的面積為81 × 267 um2，輸出訊號之最大抖動量(peak-to-peak jitter)為5.65 ps。The development and main stream of system-on-chip (SoC) are highly integration and higher operation speed. Therefore, in order to suppress the clock skew, the clock synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems. However, these circuits have to consider some problems in using. First, the PLL and DLL have issues of loop bandwidth because they are both closed loop systems. For this reason, they need to consider the loop stability problem of circuits. Second, they need more time to synchronize the input and output clock signals. It consumes a lot of power in the process of locking. Consequently, the synchronous mirror delay (SMD) circuits were developed to solve above problem.However, there are some drawbacks in conventional SMD. The phase error will increase because of the various output loading. Moreover, they cannot generate multi-phase out and the poor timing resolution due to the delay cell. A four-phase high precision fast locking synchronization mirror delay circuit is proposed in the thesis. Which not only keeps the advantage of SMD, fast locking and stability issue, but also have four-phase and high resolution output. The chip is designed in a 90-nm CMOS process and the supply voltage is 1.2V. It operation frequency range is from 690 MHz to 1.38 GHz. The chip consumes 30mW power when the operating frequency is 1.38GHz. The chip area with I/O pads is 542 × 583 um2 . Internal active area without I/O pads is 81 × 267 um2. The maximum peak-to-peak jitter is 5.65 ps.
顯示於類別:	[電機工程研究所] 博碩士論文

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