隨著製程的演進，在類比積體電路設計中，實現精確的電容比例是一項很重要的議題，尤其是類比/數位轉換器及切換式電容。在類比積體電路製造過程中，製程變異通常會造成元件的不匹配。不匹配現象主要分成兩類：系統性不匹配和隨機性不匹配。造成系統性不匹配的主要原因是在擺置時，元件呈現不對稱的擺放狀態而產生製程梯度，使整體的元件不匹配，甚至造成良率下降。造成隨機性不匹配的主要原因是在晶片製造過程中，隨機的波動及材料的特性會影響多項物理性質的參數，使得設計的實際功能和預期有落差。在之前的研究有提出將電容平均分散，可以將空間相關係數升高，也可有效的降低隨機性不匹配。本篇論文提出一個可降低電容比例不匹配的力導向電容擺置演算法。在初始擺置階段，我們使用有效且快速的方式產生對稱且分散的電容擺置，並於力導向演算法中，將空間相關性模型的特性應用於吸引力及排斥力，使電容移動至力平衡的位置且能增加空間相關係數。所有電容處於力平衡狀態後，我們應用最大權重二分匹配演算法於合法化階段，利用電容與格點的距離當作權重，以迅速地找出電容最適當的位置。實驗結果顯示，與使用模擬退火的演算法比較，我們的方法可以在較短的時間內產生出空間相關係數較高的電容擺置，進而降低不匹配效應。As the process technology progresses, one of the most important issues in analog designs is to achieve accurate capacitance ratios, such as analog-to-digital converters and switched-capacitor circuits. In the manufacturing process of analog integrated circuits, capacitor mismatch is usually caused by process variation. There are two types of capacitor mismatch: systematic and random mismatches. To reduce systematic mismatch, designers usually adopt a symmetry structure, to average the mismatch effects induced by process gradients. Capacitors should be distributed uniformly as possible to overcome random mismatch, which means they should exhibit the highest degree of dispersion. In this paper, we present a force-directed capacitor placement algorithm to reduce the capacitor mismatch. In the initial placement stage, we use an effective and fast way to generate a symmetric and distributed placement. In force-directed stage, the spatial correlation model is applied to the attractive and repulsive forces to let ca-pacitors equilibrium. Finally, we utilize maximum-weight bipartite matching algorithm to efficiently legalize capacitors. Experimental results show that, compared with an SA-based placement method, ours placement method uses shorter running time to generate a higher dispersion structure, which is effective to reduce random mismatch.
