基於無限相位補償技術延遲鎖相迴路之6 Gbps時脈與資料回復電路;A 6 Gbps Delay-Locked-Loop-Based Clock and Data Recovery Circuit with an Infinite Phase Compensation Technique

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Title:	基於無限相位補償技術延遲鎖相迴路之6 Gbps時脈與資料回復電路;A 6 Gbps Delay-Locked-Loop-Based Clock and Data Recovery Circuit with an Infinite Phase Compensation Technique
Authors:	姜柏阡;Jiang,Bo-Qian
Contributors:	電機工程學系
Keywords:	時脈與資料回復電路;CDR
Date:	2012-11-29
Issue Date:	2012-12-25 13:39:40 (UTC+8)
Publisher:	國立中央大學
Abstract:	隨著近年半導體迅速發展以及電腦網路的興起，不論在短距離如晶片間或是長距離如光纖通訊，資料傳遞頻寬皆日漸提升，傳統之並列傳輸方式已被串列傳輸所取代，例如電腦匯流排所使用之PCI-Express、SATA、USB，或是光纖網路之SONET等規格皆已使用串列傳輸作為介面，並且速度皆已提升至Gbps等級。本論文所實現之時脈與資料回復電路將以SATA 6 Gbps做為參考規格，採用雙迴路之架構，以延遲鎖相迴路(Delay-Locked Loop, DLL)作為主體，並使用兩組電壓控制延遲電路互相鎖定之方式達成無限相位補償，以彌補延遲範圍受限之問題。此論文使用TSMC 90nm製程實現了一6 Gbps雙迴路之時脈與資料回復電路(Clock and Data Recovery, CDR)，其中，雙迴路由鎖相迴路(Phase-Locked Loop, PLL)以及資料回復迴路(Data Recovery Loop, DR Loop)所組成，不同於鎖相迴路式時脈與資料回復電路(PLL-Based CDR)，雙迴路架構可以將資料回復電路的頻寬(Jitter Transfer Function, JTF)和鎖相迴路的抖動壓抑分開設計。資料回復電路使用延遲鎖相迴路對齊輸入資料和時脈訊號，但資料若有頻率誤差時，延遲鎖相迴路將因延遲範圍受限制而產生誤動作，因此，此論文提出一無限相位補償之延遲鎖相迴路(Infinitely Phase-Compensated DLL, IPDLL)，利用兩互補的壓控延遲電路適時交換，使得相位追鎖可以延續，解決傳統壓控延遲電路面臨操作範受限之問題。此外，以延遲鎖相迴路作為資料回復電路，具有快速鎖定、沒有抖動峰值以及沒有抖動累積等特點。根據設計及模擬結果，抖動轉移函數頻寬落於4.2±2 MHz，在3 nH模擬打線電感下，均方根值抖動為1.73 ps，峰對峰值抖動為7.77 ps，資料回復迴路及鎖相迴路所占面積分別為0.11及0.045mm2，在1.2V之供應電壓下之功率消耗為79.8 mW。In recent year, according to the rapid evolution of process and computer network development, the various bandwidth requirement such as short distance like chip-to-chip communication and long distance like fiber-optic communication is increased. The use of serial data transmission substitute for the parallel one. The serial data transmission are widely used for bus in computer such as PCI-Express, SATA, USB, and used for fiber-optic network like SONET. Most of these systems adopted the serial link architecture and operate at gigahertz. This study presents a clock and data recovery (CDR), and takes SATA 6 Gbps specification as reference material. The CDR employs the Delay-Locked Loop (DLL) as data recovery (DR) loop which consists of two sets of complementary voltage-controlled delay line (VCDL). It can solve the problem of delay range limitation. This study presents the CDR circuit fabricated in a 90-nm CMOS process. The dual-loop-based CDR consists of a phase-locked loop (PLL) and a DR loop. Unlike the commonly used PLL-based CDR, the bandwidth for the clock jitter suppression and the specific jitter transfer function (JTF) could be optimized through the PLL and DR loop, respectively. With regard to the DR loop, the DLL could be used for the phase alignment between the input data and the clock signal. However, once the input data accompanies the frequency offset, the DLL may suffer from the limitation of the finite phase tracking range, resulting in the erroneous function. Thus, this study proposes a infinitely phase-compensated DLL (IPDLL), which correlates and swaps the two complementary VCDL if necessary. The IPDLL-based CDR generates the continuous clock phase shifts for data tracking to resolve the operating range limitation of the convenient DLL control scheme. In addition, it exhibits the fast-locking, jitter-peaking-, and jitter-accumulation-free characteristic. As a result, in terms of the CDR setting, conforming that the gain of error signal E(s) of -3 dB lies at the jitter frequency of 4.2±2.1 MHz, the 6-Gb/s input data is simulated with the 3-nH wire bonding, and the RMS and peak-to-peak jitter of the recovered clock are 1.73 ps and 7.77ps, respectively. The chip core area of DR and PLL occupy 0.11 and 0.045 mm2, respectively. The total power consumption is around 79.8 mW at supply of 1.2V.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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