應用於生理訊號擷取之低雜訊類比前端電路; A Design of Low-noise Analog Frond-end Circuit for Bio-signal Acquisition

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題名:	應用於生理訊號擷取之低雜訊類比前端電路;A Design of Low-noise Analog Frond-end Circuit for Bio-signal Acquisition
作者:	楊善淇;Yang,Shan-chi
貢獻者:	電機工程學系
關鍵詞:	虛擬電阻;生理訊號放大器;電流轉導式放大器;pseudo-resistor;biomedical sensor interface
日期:	2013-07-20
上傳時間:	2013-08-22 12:13:07 (UTC+8)
出版者:	國立中央大學
摘要:	隨著現代醫學的發達，可攜帶的生醫訊號量測裝置是目前的趨勢，我們希望病人可以攜帶輕巧的監控裝置並可長時間的監控生理狀態。近幾年來不同生醫應用層面的生理訊號量測系統發展趨向於微小化並搭配無線方式傳輸訊號。本篇主旨為提出一應用於生醫訊號量測系統之低雜訊前端類比前端電路，可針對不同生醫訊號如腦波圖(Electroencephalography, EEG)、心電圖(Electrocardiography, ECG)訊號作記錄。為了將其中低頻的非理想如直流偏移電壓、閃爍雜訊等影響減小，並考量電路為on chip設計，我們設計一可調性虛擬電阻用來形成極低頻之極點，克服形成低頻極點需要大電阻的問題，並且改善製程變異與共模電壓的飄移。為了降低整體電路的功率消耗及減低熱雜訊，將放大器輸入級的場效電晶體操作於弱反轉區可以比電晶體操作在飽和區有更好的表現，整體電路以高解析度、低功耗及低雜訊為設計目標。本文所提整體類比前端電路包含偏壓電路、可調式虛擬電阻、ac 耦合式帶通濾波器、共模回授電路。在電路實現上，在輸入訊號頻率1 kHz、150 μV輸入振幅下，整體放大器增益為72 dB，而在輸入訊號200 Hz，2 mV的輸入振幅下，放大器增益為58 dB，可調低頻截止點範圍為4 Hz到300 Hz，輸入相關雜訊為3.61 μVrms，整體總諧波失真為60.21 dB，雜訊效率因素(Noise efficiency factor)為4.7。搭配後端三角積分調變器出來的整體SNDR (Signal to Noise-Distortion Ratio)為65 dB，其有效位元數為10位元的解析度。我們使用台積電0.18 μm CMOS 1P6M製程，其晶片面積約佔0.68 mm2。在1.8 V電源供應下，整體晶片消耗之功率約為55 μW。 With the advances in modern medicine, portable bio-medical measurement device is the current trend. We hope that the patient can carry light device for a long time monitoring. In recent years, the bio-signal measurement devices for various bio-medical applications trend to be minimized and with wireless transmission capabilities. This work presents a low noise analog-front-end circuit for bio-signal measurement system that can be used to record different bio-signal such as Electronencephalogram (EEG) and Electrocardiography (ECG) signals. When circuit operates at low frequencies, we need a tunable pseudo-resistor with a huge resistance to form a very low frequency pole to minimize the non-ideal effect such as DC-offset, flicker noise, and on chip design. Then, the pseudo-resistor can resolve process variation and DC-offset from electrode. In addition, in order to reduce the power consumption and thermal noise effect, the input stage MOS of the operation amplifier are designed to operate at the weak-inversion region and to get better performance than MOS operate in saturation. The AFE circuit is aiming at low power consumption, low-noise, and high resolution. The whole AFE circuit includes a bias circuit, pseudo-resistor, ac coupling band-pass filter, and common-mode feedback circuit. When the input signal is 1 kHz sine wave with 150 μV amplitude, the AFE achieves mid-band gain of 72 dB, and when the input signal is 200 Hz sine wave with 2 mV amplitude, the AFE achieves mid-band gain of 58 dB. The programmable low-cutoff frequency ranges from 4 to 300 Hz the input referred noise is 3.61 μVrms and the THD is 60.2 dB. The circuit is fabricated in the TSMC 0.18-μm one-poly six metals CMOS process, and the chip area is 0.68 mm2. The simulated power consumption is about 55 μW for 1.8 V power supply.
顯示於類別:	[電機工程研究所] 博碩士論文

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