本論文利用tsmcTM的不同矽製程（0.18 m 與90 nm）設計功率放大器，在設計上分成兩部份，第一部份為tsmcTM 0.18 m CMOS製程設計功率放大器以操作於C頻帶寬頻功率放大器為主要目標。電晶體使用串疊方式。運用電抗補償技術與負電容補償方法，搭配E類開關式功率放大器具有高效率輸出的優勢，達成高效率與寬頻E類功率放大器的目標；第二部份，由於高階製程技術不斷推陳出新，電晶體的操作頻率也可大大獲得提升。實作全積體整合矽製程tsmcTM 90 nm CMOS設計於V頻段之高增益與寬頻功率放大器，使用寬頻匹配技術與增益提升技術，搭配串接三級電晶體串疊架構與審慎的級間匹配考量達到寬頻與高增益的目標。 各電路特性量測如下：C頻段高效率技術CMOS 之E類寬頻功率放大器，增益量測結果為5.45 dB，飽和輸出功率為22 dBm，效率為19.71%；V頻段CMOS之高增益與寬頻功率放大器，增益量測為21.8 dB，1-dB增益壓縮點輸出功率為8.1 dBm，飽和輸出功率為12.75 dBm，功率增進效率（PAE）為10.75%，3-dB頻寬為16 GHz（54 GHz to 70 GHz）。 Both the C-band and V-band fully integrated silicon-based power amplifiers are designed in the thesis, using 0.18 m and 90 nm CMOS processes by tsmcTM, respectively. In the first part, reactance compensation network is adopted for the circuit design for wideband consideration a 5-6 GHz class-E high efficiency power amplifier was implemented. In the second part, a high gain and wideband V-band power amplifier was implemented by adopting wideband matching network technique. Measurement results are summarized below: The 5-6 GHz class-E power amplifier fabricated in 0.18 m CMOS technology achieves a power gain of 5.45 dB, a saturation output power of 22.79 dBm, and a power-added-efficiency of 19.71%. The V-band power amplifier with high gain and wide-band in 90 nm CMOS Technology achieves a power gain of 21.8 dB, an output power at 1-dB gain compression point of 8.1 dBm, a saturation output power of 12.75 dBm, and a power-added-efficiency of 10.75%.
