研究期間：10108~10207;As the manufacturing process advances, the size of integrated circuits has shrunk into the 32 nm. Lithography process encounters a bottleneck due to printability and manufacturability issues. Recently, double patterning lithography (DPL) has been proposed for the most feasible solution for sub-32-nm node process. To increase the half-pitch resolution and improve depth of focus, DPL decomposes a layout into two masks by using current infrastructures. The conflict of DPL means that a layout cannot be decomposed completely, and then the un-decomposable pattern must be partitioned into two sub-patterns. These two sub-patterns should be assigned to different masks and connected to each other. The touching edge of sub-patterns is called stitch. If there is no enough space to insert a stitch for the un-decomposable pattern, a native conflict is generated. A layout with native conflicts will result in layout modification. The current researches focus on reducing the number of stitches and the number of native conflicts in the post layout phase or detailed routing phase. Since the layout is more and more complicated, considering DPL before detailed routing and alleviating the loading in detailed routing will be a challenge. In this project, we propose a method to consider DPL in track routing. Besides, we propose a pseudo pin technique to avoid generating a lot of native conflicts in track routing and predict the traces of detailed routing.