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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/65835

    Title: 考量製程變異與佈局效應的低壓降線性穩壓器自動化合成工具;Automatic Synthesis Tool for Low Dropout Regulator Considering Process Variations and Layout Effects
    Authors: 張馨如;Chang,Hsing-Ju
    Contributors: 電機工程學系
    Keywords: 低壓降線性穩壓器;自動化合成工具;製程變異;佈局效應
    Date: 2014-08-27
    Issue Date: 2014-10-15 17:11:25 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 隨著可攜式電子產品市場的盛行,為延長電池的工作時間,低功率成為可攜式電子產品的首要考量,而電源管理IC的需求也日漸增加。此外,由於日益激烈的市場競爭及緊縮的產品上市時間,高良率成為產業所追求的目標之一,因此一套可有效提升良率且縮短設計時間的自動化合成工具是必不可少的。

    本論文提出一套考量製程變異與佈局效應的低壓降線性穩壓器自動化合成工具,可經由人性化的圖形介面,設計出符合需求規格的電路設計與電路佈局。為了提高良率評估的精準度,本論文以最壞情況距離(worst case distance)的概念來協助訂定良率的目標,並與布局效應一起整合到以方程式為基礎的自動化設計流程中,在自動化流程中並同時考慮誤差放大器(Error amplifier)和低壓降線性穩壓器的交互效應,以達成整體電路的最佳化,降低設計的成本。

    本論文中的自動化合成工具已在Linux上實現,在線性規劃(linear programming)的部分使用CPLEX來找尋最佳解,而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言產生批次命令,再由Laker自動完成佈局的過程。從實驗數據的觀察可知,本論文所提出的工具可快速設計出符合使用者所給定規格之電路,在佈局後電路效能皆可達到所需求的規格,並可有效提升電路良率,達成高品質的需求。

    ;With the increasing demand of portable electronic devices, reducing power consumption has become the major concern to increase the battery life. The demand of power management ICs are also increasing in those electronic products. Moreover, due to the fierce market competition and the need of fast time-to-market, high design yield is also one of the major objectives in industry. Therefore, an automated synthesis tool is essential to shorten the design cycles and improve the design yield.

    This thesis presents an automatic synthesis tool for low dropout regulator (LDO) considering process variations and layout effects. This tool can generate the required designs from specifications to layout through a user-friendly GUI. In order to optimize the design yield with accurate variation consideration, the worst case distance (WCD) concept is integrated into the layout-aware equation-based sizing approach in this work. The device in the low dropout linear regulator and its error amplifier are both considered in the optimization process for reducing the overall circuit cost.

    The proposed sizing algorithm has been implemented in Linux with the LP solver CPLEX, incorporating with an automatic layout generation tool implemented with C/C++ and Tcl/Tk on Laker. As demonstrated in the experimental results, this synthesis tool is able to achieve the required specifications in a short time and significantly improve the design yield while the post-layout performance is still guaranteed.
    Appears in Collections:[電機工程研究所] 博碩士論文

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