由實驗結果可知，本論文所提出的電路自動化設計流程，確實可有效考慮電路非理想效應對於電路效能之影響，並且修正電路參數，以符合電路之規格，並提升設計的良率。此外，本論文提出之設計流程亦可達到較小的電路面積與功率消耗，並能依使用者之需求彈性調整目標。相信如此的方式，能幫助設計者面對深次微米製程的挑戰，並加速電路設計之流程。;With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. If those non-ideal effects can be considered in the early design stage, the re-design and re-spin cost can be avoided. Thus, a reliable design flow from specification to fabrication is presented, which consider parasitic effects, process variations, and aging effects.
Firstly, a layout-aware automated design flow is proposed in this dissertation to consider the layout-induced parasitic effects based on a flexible layout template. Therefore, the case that the performance fails to meet the specifications after layout can be avoided.
Secondly, a modified equation-based variance analysis method is proposed to calculate each performance variations without simulations. It can be used to improve the accuracy of yield prediction for each possible solution in equation-based optimization. This design flow enables simultaneously optimization with other design objectives like power or area cost to prevent unnecessary over-design.
Finally, a hierarchical reliability analysis and a reliable design flow is proposed to estimate the performance degradation considering process variations and aging effects simultaneously. With the fast and accurate prediction of degradation effects, the fresh yield and lifetime yield are considered simultaneously at the sizing stage.
As shown in the experimental results, the proposed method ensures the performance after layout due to accurate prediction the parasitic effects. Also, this design flow can further improve the fresh yield and lifetime yield, and the design overhead is reduced significantly with within a fast computation time.