近年來由於網路和處理器的快速發展，使得快速傳輸大量資料成為傳輸系統的主要動機，因此傳統的平行匯流排逐漸的被高速串列傳輸系統所取代。但是，當系統的操作頻率在億兆赫茲時，高頻的資料經過通道之後會失真及衰減。為了迎合電子產品低成本和低功率的需求，本論文提出一個具可關閉自我斜率偵測機制之低功率低成本適應性等化器來補償通道的損失。 為了降低功率消耗和面積成本，除了數位化，最有效的方法是減少和關閉高速電路，所以提出了串列處理的想法來減少高速檢測電路，這個主要的概念是使用自我斜率偵測器去偵測兩個連續的斜率，而不是傳統利用截剪器(Slicer)再使用檢測電路去偵測兩個平行斜率，而此概念詳細的作法就是將整個包含控制電路的偵測電路數位化並使用邏輯電路和暫存器來實現。補償完畢後，關閉機制會關閉偵測電路和數位控制電路來減少功率消耗。而且使用串列處理，訊號會經過相同的電路和相同的路徑，可以避免擺幅不平衡的問題或是走線不匹配的問題。 本晶片以 TSMC 90-nm 1P9M CMOS 製程來實現，在工作電壓為1-V，並關閉偵測機制時，其功率消耗為 4.35-mW (不含輸出緩衝器)，當晶片包含焊墊(Pad)時，晶片總面積為 0.6724-mm2，而核心部分的面積為 0.1-mm2 (不含輸出緩衝器)。在經過1.3公尺的通道，輸入5-Gb/s PRBS31的訊號時，輸出峰對峰的抖動量為0.28-UI。 ;In recent years, due to rapid developments of the network and the processor, transmitting a lot of data becomes the main motivation of transmission system. Therefore, the conventional parallel bus is replaced by the high-speed serial link transmission system gradually. However, when system operates at gigahertz level frequency and the signal passes through the channel, the high frequency signal distorts and degrades. For demand of low cost and low power consumption for the consumer electronic products, this research proposes a low-power adaptive equalizer with closeable digital-control self-slope detection to compensate channel loss. In order to reduce both power and cost, in addition to digitizing, the most effective ways are reducing and closing the high-speed circuit. The idea of serial processing is proposed to reduce one high speed detection circuit. The main concept is using the self-slope detection circuit which compares two continuous serial slopes by itself instead of the conventional detection circuit which uses slicer. The proposed detection circuit, including control circuit, is digitizing and using the register and the logic circuit. After compensation, the shutdown mechanism turns the control circuit off to reduce power. By serial processing, the data passes the same circuit and the same path to avoid swing balancing issue and mismatch. The equalizer chip is implemented in TSMC 90-nm 1P9M CMOS technology. The equalizer works at supply power 1-V with 4.35-mW (excluding the output buffer) enabled shutdown mechanism. The total chip area is 0.6724-mm2 with pads, and the core area is 0.023-mm2 (excluding output buffer). The measured peak-to-peak jitter is 2.55-UI at 5-Gb/s by PRBS31 pattern through a 1.3-m channel.
