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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/66907

    Title: 具可關閉數位控制式自我斜率偵測機制 之低功率適應性等化器;A Low-power Adaptive Equalizer with Closeable Digital-control Self-slope Detection
    Authors: 李曼如;Lee,Man-Ju
    Contributors: 電機工程學系
    Keywords: 等化器;數位;低功率;自我斜率偵測機制;適應性;Low-power;Equalizer;Digital;Self-slope Detection;Adaptive
    Date: 2015-01-23
    Issue Date: 2015-03-16 15:59:07 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 近年來由於網路和處理器的快速發展,使得快速傳輸大量資料成為傳輸系統的主要動機,因此傳統的平行匯流排逐漸的被高速串列傳輸系統所取代。但是,當系統的操作頻率在億兆赫茲時,高頻的資料經過通道之後會失真及衰減。為了迎合電子產品低成本和低功率的需求,本論文提出一個具可關閉自我斜率偵測機制之低功率低成本適應性等化器來補償通道的損失。
    本晶片以 TSMC 90-nm 1P9M CMOS 製程來實現,在工作電壓為1-V,並關閉偵測機制時,其功率消耗為 4.35-mW (不含輸出緩衝器),當晶片包含焊墊(Pad)時,晶片總面積為 0.6724-mm2,而核心部分的面積為 0.1-mm2 (不含輸出緩衝器)。在經過1.3公尺的通道,輸入5-Gb/s PRBS31的訊號時,輸出峰對峰的抖動量為0.28-UI。
    ;In recent years, due to rapid developments of the network and the processor, transmitting a lot of data becomes the main motivation of transmission system. Therefore, the conventional parallel bus is replaced by the high-speed serial link transmission system gradually. However, when system operates at gigahertz level frequency and the signal passes through the channel, the high frequency signal distorts and degrades. For demand of low cost and low power consumption for the consumer electronic products, this research proposes a low-power adaptive equalizer with closeable digital-control self-slope detection to compensate channel loss.
    In order to reduce both power and cost, in addition to digitizing, the most effective ways are reducing and closing the high-speed circuit. The idea of serial processing is proposed to reduce one high speed detection circuit. The main concept is using the self-slope detection circuit which compares two continuous serial slopes by itself instead of the conventional detection circuit which uses slicer. The proposed detection circuit, including control circuit, is digitizing and using the register and the logic circuit. After compensation, the shutdown mechanism turns the control circuit off to reduce power. By serial processing, the data passes the same circuit and the same path to avoid swing balancing issue and mismatch.
    The equalizer chip is implemented in TSMC 90-nm 1P9M CMOS technology. The equalizer works at supply power 1-V with 4.35-mW (excluding the output buffer) enabled shutdown mechanism. The total chip area is 0.6724-mm2 with pads, and the core area is 0.023-mm2 (excluding output buffer). The measured peak-to-peak jitter is 2.55-UI at 5-Gb/s by PRBS31 pattern through a 1.3-m channel.
    Appears in Collections:[電機工程研究所] 博碩士論文

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