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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68737

    Title: 串聯電阻陣列之金屬層可交換式平衡繞線
    Authors: 翁銘聖;Weng,Ming-Sheng
    Contributors: 電機工程學系
    Keywords: 任意排列;串聯電阻陣列;自動化佈局;繞線;寄生效應平衡;Arbitrarily permutation;Series resistor array;Automation layout;Routing;Parasitic effects balance
    Date: 2015-07-13
    Issue Date: 2015-09-23 14:22:49 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 因為半導體製程技術不斷進步,所以製程變動(process variation)造成元件不匹配(mismatch)與導線寄生效應的變動也越趨嚴重。此外,類比電路在設計上的複雜度與時間成本越來越高,因此是否能有可靠的自動化實體佈局將會成為提升整體電路設計效率的關鍵。

    在電阻串聯式數位/類比轉換器電路中,串聯電阻陣列用來提供轉換電路連續參考偏壓,藉由電阻串陣列的排列與空間相關性提昇電阻本身在抑制製程變異的能力,也可以有效的降低電路的隨機誤差(random error),然而,高精確度電阻串及電阻串陣列本身的排列擺置,皆會提高其在實體佈局中繞線上的困難度,導線寄生阻值(interconnect)的不一致性將會引起電路的系統誤差(systematic error),所以一個好的排列,若未能在實體佈局上自動化實現與平衡寄生效應,終將功虧一簣,故自動化繞線與導線寄生阻值平衡皆不可或缺。

    本論文中利用不同金屬層彼此交換作為補償,並且確保每一條電阻間的導線都具有相同的水平與垂直金屬層分配(IC-level channel routing)、相同的VIA區塊、一致的電阻連接形式。接著我們以電阻陣列對角的繞線路徑為基準,並將所有的繞線路徑延伸至等長,且同時開發一個圖型使用者介面(GUI)工具,提供使用者做繞線資訊的設定。佈局完成後再透過calibre軟體來驗證寄生阻值的一致性。
    ;Because of the progress of the semiconductor process technology, the process variation will be more and more serious in device mismatch and wire parasitic. In addition, analog circuit design increase time-consuming and complex, so a reliable automation tool will become the key point to enhance the efficiency of the overall circuit design.

    For the series resistor array in resistor-string DAC, we can effectively reduce the random error by the permutation and space correlation of resistors. However, the high precision resistor string and resistor array permutation will increase the difficulty of the physical layout, and the inconsistency of the parasitic resistance will cause the circuit system error. Therefore, a good arrangement can not be achieved in the physical layout automation and balance parasitic effects, it will eventually fall short. In other words, the automated routing and interconnect resistance balance has already indispensable.

    In this thesis, we get the compensation by exchanging two layer and ensure that each resistor connected wires having the same layer distribution, the same number of VIA block, and the consistent connection form. Then we stretch all routing paths to the same total length. The standard of length is the diagonal routing path. While developing a graphical user interface (GUI) tool, it can provide users to set routing information, bit number, and type clearly. Finally, we balanced the parasitic resistance by calibre.
    Appears in Collections:[電機工程研究所] 博碩士論文

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