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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/68777


    Title: 可靠度導向之類比積體電路擺置;Reliability-Driven Placement for Analog Integrated Circuits
    Authors: 劉宗祐;Liu,Tsung-Yu
    Contributors: 電機工程學系
    Keywords: 實體設計;類比擺置;physical design;analog placement
    Date: 2015-07-20
    Issue Date: 2015-09-23 14:25:47 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 由於類比電路的敏感性,在元件尺寸大幅地縮小之後,考量佈局後的非理想效應以及可靠度顯得更為重要。為降低非理想效應對電路效能的影響與提升可靠度,類比電路設計大多以人工的方式產生佈局,雖然使用類比設計自動化搭配工程師的佈局經驗可以取代部分人工以節省設計工作量,但眾多的佈局限制仍然是類比設計自動化發展的最大難題。
    目前存在許多類比元件擺置的相關文獻,然而同時考慮到可靠度與繞線的研究卻非常稀少。為降低製程變異以及非理想效應對佈局產生的影響,一般常建立拓樸限制處理元件之間的不匹配,但是繞線仍會產生非理想效應。為減少繞線對可靠度與電路效能的影響,繞線時應避免過窄的導線寬度與導線直角轉彎所造成電子遷移的現象,以及線長過長的導線所造成的線阻、寄生電阻電容值變大與訊號延遲。因此在擺置過程中必須要精準地預留繞線空間,考慮導線斜角轉彎與較寬的導線寬度所需要的空間,以及縮短導線總線長等因素,以確保電路能達到預定規格且擁有良好的壽命。
    本論文提出一個在擺置階段考量可靠度的類比自動化設計流程。擺置過程中首先針對繞線路徑、導線轉彎角與寬度較寬的導線預留空間,接著再使用二階段形狀曲線修剪技巧,留下導線總線長較短、面積較小的擺置結果,最後應用延遲決策技術產生符合規格的複數擺置結果,提供使用者良好且彈性的選擇。
    ;Due to the sensitivity of analog components, both post-layout non-ideal effects and reliability are getting important with the size shrink of components. In order to reduce the impact of non-ideal effects on circuit performance and increase the reliability, the layouts of analog circuits are often generated manually. Although some EDA tools based on designer experience are available now to reduce design efforts, the complex layout constraints are still big issues for developing EDA tools.
    There are many literatures on analog placement, but the number of researches on analog placement considering both reliability and routing are few. In order to reduce the impacts on the layout caused by the process variations and non-ideal effects, topology constraints are often used to reduce the mismatch between devices. However, the non-ideal effects may still exist in the routing paths. In order to reduce the impacts from routing paths on reliability and circuit performance, narrow wires, right-angle corner bend and long wires should be avoided in the routing paths. It implies that preserving routing space accurately during placement stage is required to ensure the performance and lifetime of the circuits.
    This work presents an analog placement flow for analog circuits with reliability consideration. First, proper routing space is preserved for routing paths, corner bends and wide wires. Then, a two-stage curve pruning technology is proposed to obtain the placement results with shorter wire-length and smaller area. Finally adopting deferred decision making (DDM) technique, multiple flexible solutions can be provided for designers.
    Appears in Collections:[電機工程研究所] 博碩士論文

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