應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製;Implementation on Fully Integrated Wideband CMOS Low Power Down Conversion Mixer and Up Conversion Power Mixer for C/X Band Applications

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題名:	應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製;Implementation on Fully Integrated Wideband CMOS Low Power Down Conversion Mixer and Up Conversion Power Mixer for C/X Band Applications
作者:	陳宥任;Chen,Yu-Jen
貢獻者:	電機工程學系
關鍵詞:	低功耗降頻器;功率升頻器;Low power down conversion mixer;Power up mixer
日期:	2015-07-28
上傳時間:	2015-09-23 14:44:51 (UTC+8)
出版者:	國立中央大學
摘要:	論文名稱:應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製校所組別:國立中央大學電機工程學系研究所電波組研究生:陳宥任指導教授:邱煥凱博士摘要本論文主要分兩部份，第一部分研究C/X頻段寬頻低功耗混頻器，共實做兩顆晶片，第一顆利用tsmcTM 0.18 µm CMOS製程，使用倍頻電路架構以獲得偶次項諧波，實現次諧波混頻器，並使用源極注入技術，提升轉換增益，最後實現一寬頻低功耗次諧波降頻器。量測結果顯示，當本地振盪功率為 -1 dBm時，轉換增益為 -8.9 dB，輸入功率1-dB壓縮點為 -10.8 dBm，二階交互調變失真點為13.9 dBm，三階交互調變失真點為 -1 dBm，雙邊帶雜訊指數為12.72 dB，頻寬為5-12 GHz，直流功率消耗為6.5 mW，晶片面積為0.788×1.165 mm2。第一部份第二顆晶片，利用UMC 0.18 µm CMOS製程，並使用Ruthroff-type單轉雙巴倫作射頻埠輸入匹配，以得到寬頻之響應，應用切換式偏壓技術，改善雙邊帶雜訊指數，以及基極注入達低功耗之目的，量測結果顯示本地振盪功率為 5 dBm時，轉換增益為 7.7 dB，輸入功率1-dB壓縮點為 -18 dBm，二階交互調變失真點為7.7 dBm，三階交互調變失真點為 -9.9 dBm，雙邊帶雜訊指數為10.87 dB，頻寬為5.2-12 GHz，直流功率消耗為0.37 mW，晶片面積為0.765×1.444 mm2。第二部份為設計混頻器與功率放大器結合之功率混頻器，利用tsmcTM 0.18 µm CMOS製程，使用差動式穿輸線型變壓器作耦合，實現寬頻之功率升頻器，量測結果顯示本地振盪功率為 11 dBm時，轉換增益為 20.97 dB，飽和輸出功率為15.02 dBm，輸出功率1-dB壓縮點功率為13.06 dBm，三階輸入交互調變失真點為3.26 dBm，三階輸出交互調變失真點為22.94 dBm，汲極端效率為10.3%，頻寬為5-12 GHz，直流功率消耗為171.68 mW，晶片面積為0.962×1.572 mm2。 ;Title : Implementation on Fully Integrated Wideband CMOS Low Power Down Conversion Mixer and Up Conversion Power Mixer for C/X Band Applications School : National Central University Department of Electrical Engineering Student : Yu-Jen Chen Advisor : Dr. Hwann-Kaeo Chiou Abstract This thesis consists of two parts. The first part is the research regarding a low power consumption wideband mixer. This work has realized two chips, the first chip is a sub-harmonic mixer fabricated in tsmcTM 0.18 µm CMOS process. This mixer uses a doubler to obtain even order harmonics to perform sub-harmonic mixing. Meanwhile, a source driven technique is adopted to enhance the conversion gain. The measurement results shows the performance as follow, a conversion gain of -8.9 dB, a P1dB of -10.8 dBm, an IIP2 of 13.9 dBm, an IIP3 of -1 dBm, a DSB noise figure of 12.72 dB at -1 dBm LO power. The bandwidth is 5-12 GHz. The DC power consumption is 6.5 mW. The chip size is 0.788×1.165 mm2. The second realized chip is fabricated in UMC 0.18 µm CMOS process. A Ruthroff-type single to differential balun is applied for the wideband input matching. The switched biasing technique is for DSB noise figure improvement. And the bulk injection can reduce the power consumption. The measurement results shows the performance as follow, a conversion gain of 7.7 dB, a P1dB of -18 dBm, an IIP2 of 7.7 dBm, an IIP3 of -9.9 dBm, a DSB noise figure of 10.87 dB at 5 dBm LO power. The bandwidth is 5.2-12 GHz. The DC power consumption is 0.37 mW. The chip size is 0.765×1.444 mm2. A multi-function circuit incorporated with a up-mixer and a power amplifier is realized in tsmcTM 0.18 µm CMOS process. A differential transmission-line transformer is utilized for wideband power match. The measurement results achieves a conversion gain of 20.97 dB, a Psat of 15.02 dBm, an OP1dB of 13.06 dBm, an IIP3 of 3.26 dBm, an OIP3 of 22.94 dBm, a drain efficiency of 10.3% at 11 dBm LO power. The bandwidth is 5-12 GHz. And the DC power consumption is 171.68 mW. The chip size is 0.962×1.572 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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