本論文利用tsmcTM 0.18-µm製程設計功率放大器，在設計上以操作於C/X頻段功率放大器為主要目標。電路採用傳統磁耦合變壓器和傳輸線型變壓器達到寬頻與低損耗的阻抗匹配，利用交錯耦合單向化電容於疊接電路來抑制共源極組態中由於閘-汲寄生電容(Cgd)所產生的米勒效應(Miller Effects)，進而提高電路的穩定性以及傳輸增益(S21)，並使用自適應偏壓電路來改善電路的線性度以及功率回退時的功率附加效率(PAE)，達成高增益和高線性度之寬頻功率放大器。 各電路特性量測如下 : 應用變壓器與自適應偏壓電路於C/X頻段之寬頻功率放大器，傳輸增益(S21)為18 dB，飽和輸出功率為21 dBm，1-dB增益壓縮點輸出功率為14.6 dBm，功率附加增益為6.33%，3-dB頻寬為1.55 GHz (5.55-7.1 GHz)，比例頻寬為24.5%；應用傳輸線型變壓器與自適應偏壓之單向化功率放大器，傳輸增益(S21)為28.27 dB，飽和輸出功率為22.95 dBm，最佳功率附加增益為23.94%，1-dB增益壓縮點輸出功率為21.77 dBm，1-dB增益壓縮點的功率附加增益最高可達21.31%，小訊號增益之3-dB頻寬為6.6 GHz (5.1-11.7 GHz)，比例頻寬為78.57%，飽和輸出功率之1-dB頻寬為6 GHz (5-11 GHz)。 ;Both C-band and X-band fully integrated silicon-based power amplifiers (PA) are designed in this thesis, which are fabricated in tsmcTM 0.18-µm CMOS Process. A CMOS PA with wideband, high gain and high linearity adopted magnetically coupled transformer and differential Guanella-type transmission-line transformers (DTLTs) is designed to achieve broadband and low loss matching. The capacitive neutralization technique is adopted to mitigate the Miller effects to improve power gain and enhance stability. The linearity and power added efficiency (PAE) at back-off region are enhanced by adaptive bias technique. The measurement results of the first PA shows a power gain of 18 dB, a saturated output power of 21 dBm, an output 1-dB gain compression point of 14.6 dBm and the maximum power added efficiency of 6.33%. The 3-dB bandwidth is from 5.55 to 7.1 GHz. The chip size is 1.57 mm2. The second PA achieves a power gain of 28.27 dB, a saturated output power of 22.95 dBm, a maximum power added efficiency of 23.94%, an output 1-dB gain compression point of 21.77 dBm with power added efficiency of 21.31%. The 3-dB bandwidth is from 5.1 to 11.7 GHz. The 3-dB bandwidth of saturation power is from 5 to 11 GHz. The chip area is 1.87 mm2
