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|Title: ||應用磁耦合變壓器技術之雙頻帶金氧半導體壓控振盪器暨5 GHz壓控振盪器與除頻器整合電路;CMOS Voltage Controlled Oscillator with Magnetically Coupled Transformer Switch for Dual-band Application and 5 GHz VCO and Divider Integrated Circuit|
|Keywords: ||壓控振盪器;雙頻;除頻器;VCO;Dual band;divider|
|Issue Date: ||2015-09-23 14:46:04 (UTC+8)|
|Abstract: ||本文利用tsmcTM 0.18 m製程技術來進行本地振盪源電路的相關設計；本論文探討現今雙頻操作振盪器的機制，設計運用磁耦合變壓器切換技術達到雙頻操作的壓控振盪器，結合不同的架構達到低功耗、低相位雜訊的目標，同時以實作的量測結果，驗證電路理論設計之正確性。其設計內容包含三個電路，內容如下所述:|
利用磁耦合變壓器切換技術，可以縮減面積以及讓調頻的頻率逐步遞增，電路的調頻範圍可以從5.55 GHz調到10.26 GHz，相位雜訊在偏移1 MHz處為-105.71 dBc/Hz，電路功耗為3.2 mW，電路的優化指標（FoMT）為-192.18；晶片面積為0.752 × 0.8 mm2。
本電路結合磁耦合變壓器切換的技術以及考畢茲、電流再利用的架構，加入源極退化電感，以增加可調頻寬以及簡化直流偏壓設計。兩個頻段的可調頻率範圍分別為5.24 GHz – 5.48 GHz以及10.4 GHz – 11.55 GHz，功耗為1.95 mW，相位雜訊在偏移1 MHz的地方為-114.9以及 -105.35 dBc/Hz，電路的優化指標在兩個頻段分別為-185.1以及-183.38；整體的晶片面積為0.842 × 0.732 mm2。
本電路包含一顆寬頻與低相位雜訊的壓控振盪器以及改良後的電流模態除頻器；壓控振盪器的可調頻率範圍為4.68 GHz – 6.19 GHz，對應的除頻範圍為2.34 GHz – 3.1 GHz，直流功耗為2.52 與3.75 mW；相位雜訊在偏移1 MHz的地方為-117.1 以及-122.3 dBc/Hz。整體的晶片面積為0.73 × 1.16 mm2。
;As more increasing demands for low-cost in wireless communication system, multi-standards circuits are proposed to support the requirements. Therefore, RF transceivers become more complex and consume more power to satisfy the different wireless systems, which means that various kinds of local sources are needed meanwhile. Since voltage controlled oscillator (VCO) is an important sub-circuit in phase locked loop (PLL), this thesis includes five parts, which are motivation, two VCOs for dual-band application, integrated circuits for 5GHz and future work.
Chapter 1 illustrates the motivation of the system standards. And chapter 2 introduces the basic theory of transformer and implements a transformer-switch based VCO for dual-band and wideband application fabricated in 0.18-μm CMOS technology. This design uses the transformer not only for reducing the chip size, but also enabling the center frequency tunable monotonically. By setting the different bias, the circuit can be operated as dual-band or wideband. The measured tunable oscillation frequency is from 5.55 GHz to 10.26 GHz. The power consumption is 3.2 mW and the phase noise is -105.71 dBc/Hz at 1-MHz offset respectively. The obtained FoMT is -192.18. The chip area, including RF signal pads and DC bias pads, is 0.752 × 0.8 mm2.
Chapter 3 presents a Colpitts with current-reused technology. The Colpitts current-reused VCO fabricated in 0.18-μm CMOS technology with magnetically coupled switch. The design procedure and measurements are described in this chapter. This circuit adopts the source degeneration inductor to extend the tuning range and eases the design of DC bias simultaneously. The measured center frequencies for each sub-band are 5.36 GHz and 10.95 GHz with tunable from 5.24 GHz to 5.48 GHz and 10.4 GHz to 11.5 GHz. The phase noise are -114.9 and -105.35 dBc/Hz, respectively. The total power consumption is 1.95 mW. The FoM are -185.1 and -183.38, respectively. The chip area, including RF signal pads and DC bias pads, is 0.842 × 0.732 mm2.
Chapter 4 then reviews the conventional design of frequency dividers. A VCO is integrated with frequency divider in this chapter. The oscillator can be tuned from 4.68 GHz to 6.19 GHz, the corresponding output frequency of divider is 2.34 GHz to 3.1 GHz. The power consumptions are 2.52 and 3.75 mW. The phase noise are -117.1 and -122.3 dBc/Hz respectively. The chip area, including RF signal pads and DC bias pads, is 0.73 × 1.16 mm2.
Chapter 5 concludes the aforementioned three designs and brings up the future work in the end of the thesis.
|Appears in Collections:||[電機工程研究所] 博碩士論文|
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