本論文之寬頻操作鎖相迴路使用90 nm CMOS製程實現晶片，供應電壓為1 V，鎖相迴路輸出時脈為0.8 GHz ~ 2.7 GHz，而三倍頻器輸出時脈為2.4 GHz ~ 8.1 GHz，所有頻率的方均根抖動(JitterRMS)表現皆小於5%時脈週期，在頻寬效正的部分，在1 MHz位置的相位雜訊最大的改善量為10 dBc/Hz，此時的輸出頻率為2.7 GHz。整體晶片所佔面積為1.20 mm2，電路所佔面積為0.048 mm2，電路操作在最高頻率時的功率消耗為13.9 mW。 ;A 0.8 ~ 8.1 GHz wide range phase-locked loop (WRPLL) with bandwidth calibration mechanism is proposed. In this thesis, triple-push technique is used to extend the oscillator tuning range without influence the stability of phase-locked loop. Furthermore, it can relieve difficulties effectively in design loop bandwidth for wide range application. For the weakness of the tripler output power, differential structure are used in oscillator and tripler to enhance 3rd harmonic energy. The output swing of tripler is about twice as large as the traditional single-ended structure. The off-chip control signals are used to adjust both divider ratio and charge pump current in order to maintain the bandwidth and stability across the operating range. In a addition, instead of using any other phase averaging techniques, this thesis proposed a highly symmetric layout method to reduce phases mismatch without increase extra area cost.
The experiment chip of the proposed WRPLL was implemented with 90 nm CMOS process. The measured output frequency is 0.8 ~ 2.7 GHz for PLL output and 2.4 ~ 8.1 GHz for tripler output at 1.0 V supply voltage with 13.9 mW power consumption at the highest operating frequency. The maximum improvement of phase noise after bandwidth calibration is 10 dBc/Hz at 1 MHz frequency offset at 2.7 GHz output frequency. The full chip area is 1.20 mm2 and the core area is 0.048 mm2.