隨著半導體科技日益發展，許多新穎材料正在持續地突破發展，期待能取代傳統矽材料成為次世代的半導體材料。其中，三五族化合物半導體是現今最受期待的研究主題之一，三五族材料如砷化銦擁有窄能隙及高電子遷移率之特性，使之能在低操作電壓環境下提供高導通電流，是相當適合製作未來高效能低功耗互補式電晶體之材料。然而，相較於擁有良好界面品質的矽材料，三五族化合物半導體與高介電值氧化層之間存在大量的界面缺陷將造成嚴重的載子表面散射，使元件之導通電流大幅下降，同時，閘極控制能力亦受缺陷影響而無法順利操控開關，將導致過大的功率損耗。因此，界面缺陷的清除是目前砷化銦元件發展的首要工作之一。 本論文研究首先以氫氣與氮氣電漿於沉積氧化層前進行表面處理，並製作成氧化鉿(3 nm)/氧化鋁(2 nm)/砷化銦金氧半電容，藉由電容-電壓特性探討電漿表面處理後之缺陷密度及缺陷能階分佈狀況。實驗結果顯示，氫氣電漿雖與表面氧原子間的化學反應能有效將原生氧化層之缺陷消除，但於ALD腔體之高溫環境下，將使得反應過於激烈而造成表面出現銦聚集現象，使元件發生嚴重的漏電問題；而經過氮氣電漿表面處理後，以Terman method之缺陷計算方式下，導電帶附近及能隙中間區之缺陷密度可有效地降低至2.9×1013 eV-1cm-2及2.5×1012 cm-2eV-1，並且在氧化層/半導體界面形成氮化鋁層，使閘極氧化層之絕緣性提升且提供額外的防護層，讓氧半界面在後續的製程中避免受到氧化之影響。 為了得到更低的界面缺陷密度，吾人亦於非臨場環境下結合氫氣及氮氣電漿之缺陷清理特性，發展出先以氫氣電漿清理表面氧化物和砷二聚體，再利用氮氣電漿將界面氮化之處理方式，使導電帶附近之缺陷密度再減少至2.3×1013 eV-1cm-2，並且在能隙內得到最小的缺陷密度約7.1×1011 cm-2eV-1。此研究顯示，將氫氣及氮氣電漿搭配進行界面清理後，能夠有效降低界面缺陷密度和解決費米能階釘扎效應，且在考慮氧化層與界面缺陷的情況下，吾人以氫氣搭配氮氣電漿處理之界面特性亦為當前領先的研究成果之一，其界面缺陷改善程度更優於文獻中使用化學性蝕刻之處理方式約兩個數量級，顯示此技術對於未來實現砷化銦電晶體將有相當大的助益。 ;There have been various semiconductor materials proposed so far to overcome the physical limitation of current Si-based transistor technology. Among these proposals, III-V materials are considered very promising candidates in the future. Since InAs has the advantages of having very high electron mobility for high speed operation, and narrow bandgap for low voltage operation, it attracts great attention for application in future high performance, low power consumption complementary metal-oxide-semiconductor (CMOS). However, the lack of high quality high-k/InAs interface, i.e. there exists significant amount of interface traps, which result in severe carrier scattering and poor channel modulation, has hindered the deployment of InAs metal-oxide-semiconductor field-effect-transistors (MOSFETs). To overcome the interface traps issue, a hydrogen and nitrogen plasma surface cleaning method is proposed in this work. The effects of this cleaning method on the density of interface traps (Dit) and the distribution of these traps in the energy gap are investigated by characterizing a series of HfO2/Al2O3/InAs MOS-capacitors that are subject to different plasma cleaning processes. It is found that hydrogen plasma is too aggressive and could cause In droplets on InAs surface during the device processing, while nitrogen plasma could preserve the surface and successfully reduce the traps density to 2.9× 1013 cm-2eV-1 and 2.5×1012 cm-2eV-1 near the conduction band and midgap, respectively. The presence of an AlN nitridaton layer at the interface is believed to play a role to avoid re-oxidation in the subsequent processes. In order to achieve the lowest Dit, InAs MOSFETs subject to both hydrogen and nitrogen plasma treatments are fabricated in an ex-situ environment. As a result, a low Dit of 8.3×1012 cm-2eV-1 near the valence band, 2.3×1013 cm-2eV-1 near the conduction band, and 7.1×1011 cm-2eV-1 inside the bandgap has been archieved, respectively.
