本論文使用tsmcTM 0.18-m與90-nm製程來實現收發機中本地振盪源的相關電路；本論文將先介紹自我注入式之缺點，再分析互補型之運作機制，並以此設計四項為壓控振盪器，此外整合壓控振盪器與除頻器，最後延伸至鎖相迴路之實現。本文內容包含三個電路，內容如下所述： 一、 互補型自我注入式四相位壓控振盪器之研製 本電路使用自我注入式架構實現四相位輸出，並以互補式型態改善原架構之缺點並減少功耗。電路功耗為5.23 mW，頻段的調頻範圍可以從5.11 GHz–5.87 GHz相位雜訊在偏移1 MHz處為-110.95 dBc/Hz，相位誤差為0.29，電路的優化指數(FoM、FoMQ)分別為-178.5 dBc/Hz與-228.69 dBc/Hz，晶片面積為1.12 × 0.73 mm2。 二、 使用轉導提升與電流再利用之壓控振盪器整合除頻器之研製 本電路包含一顆壓控振盪器與電流模式邏輯除頻器(CML Divider)，壓控振盪器的部分使用互補式架構提升轉導並降低相位雜訊。壓控振盪器與除頻器電路功耗分別為2.06與4.05 mW，其可調頻率範圍分別為10.52–11.66 GHz與5.26–5.82 GHz，相位雜訊在偏移1 MHz處分別為-106.7 dBc/Hz與-112.3 dBc/Hz，電路的優化指數(FoM)分別為-184.1 dBc/Hz與-178.9 dBc/Hz，晶片面積為0.68 × 0.57 mm2。 三、 X頻段鎖相迴路之研製 本電路為固定整數型鎖相迴路，總功耗為7.59 mW，鎖定範圍為10.74–10.78 GHz，參考突波及方均根時脈抖動分別為-64.71 dBc與1.41 psec，電路的優化指數(FoMSpur、FoMPower、FoMJitter)分別為92.25、0.49、-228.21，晶片面積為0.68 × 0.66 mm2。 ;In this thesis, circuits were fabricated in tsmcTM 0.18-m and 90-nm CMOS process for realizing the local oscillation source in the transceiver. This thesis will introduce the drawbacks of conventional self-injection-coupled technique, and then analyzes the operation mechanism of the complementary type. Moreover, the integration of voltage-controlled oscillator and frequency divider was realized with the same architecture to realize the phase-locked loop (PLL) circuit. The first work in Chapter 2 implements a QVCO by using self-injection-coupled technique and utilizes complementary coupled pair to resolve DC offset problem. This design was fabricated in tsmcTM 0.18-m CMOS process. The dc power consumption is 5.23 mW for a 0.75 V supply voltage. The measured tuning range is from 5.11 to 5.87 GHz. The measured phase noise is -110.95 dBc/Hz at 1 MHz offset and the phase error is 0.29. The figure of merit (FoM,FoMQ) of circuit are -178.5 dBc/Hz and -228.69 dBc/Hz, respectively. The chip area is 1.12 × 0.73 mm2. Chapter 3 presents two circuits. One of them is a VCO integrated with a frequency divider. In VCO design, complementary cross-coupled topology is adopted. The frequency divider topology is a current mode logic divider (CML). This design was fabricated in tsmcTM 90-nm CMOS process. The dc power consumption of the VCO and CML are 2.06 mW and 4.05 mW, respectively. The measured tuning range of the VCO and CML are from 10.52 to 11.66 GHz and 5.26 to 5.82 GHz, respectively. The phase noise of the VCO and CML are -106.7 dBc/Hz and -112.3 dBc/Hz at 1 MHz offset. The figure of merit (FoM) of the VCO and CML are -184.1 dBc/Hz and -178.9 dBc/Hz, respectively. The chip area is 0.68 × 0.57 mm2. The last work in Chapter 3 implements an X-band integer-N phase locked loop. This design was fabricated in tsmcTM 90-nm CMOS process. The division ratio of the PLL is 256. The total dc power consumption is 7.59 mW. The measured locking range is from 10.74 to 10.78 GHz with the reference frequency from 41.2 to 42.1 MHz. The measured bandwidth is 1 MHz. The reference spur and RMS jitter are -64.71 dBc and 1.41 ps, respectively. The power efficiency is 0.71. The figure of merit (FoMSpur, FoMPower, FoMJitter ) of circuit are 92.25, 0.49, -228.21, respectively. The chip area is 0.68 × 0.66 mm2.
