| 摘要: | 本篇論文分別利用tsmcTM 180 nm及tsmcTM 90 nm CMOS製程設計低雜訊放大器與接收機，CMOS製程的缺點為低轉導能力 ( gm )、高基板損耗、低電晶體耐壓，其中轉導能力又與雜訊指數正相關，因此雜訊指數為接收機設計的一大挑戰，為了解決轉導能力不足和基板損耗過大的問題，研究主題為如何利用變壓器寬頻設計克服轉導能力不足，並對於接收機進行雜訊分析並最佳化設計。實現的第一顆電路，係利用閘極與源極變壓器得到輸入寬頻響應，並推導變壓器耦合值對電感的關係式，藉由提升閘級電感讓高頻轉導值提升進行寬頻低雜訊放大器應用於C~X頻帶設計。另外，修改第一顆電路的體極自我偏壓設計，第二顆電路為一低功耗寬頻接收機電路應用於C~X頻帶的設計。考慮各級之間阻抗值與電壓模態、電流模態的區別，經由公式推導可以得出各級在低功耗下能表現的最佳雜訊指數。轉導能力不足的問題可由反向放大器架構器解決，使得原本共源極放大器的轉導能力能提升一倍，通道頻寬由轉阻放大器 ( Trans-impedance Amplifier, TIA ) 的RC並聯回授決定。第三顆電路為ㄧ整合I/Q接收機，使用四分之一責任週期 ( 25% Duty Cycle )本地振盪源，並將接收訊號分為I/Q通道以克服I/Q 路徑交調失真，並解決鏡像問題。
使用0.18m CMOS 設計寬頻低雜訊放大器，使用閘極與源極變壓器得到輸入寬頻響應，後級利用並聯電阻回授達到提升整體線性度的效果。量測增益為12.05 dB，頻寬為4.5 ~ 10.1 GHz，雜訊指數為3.01 dB，線性度IIP3為2.5 dBm，整體功耗為9.71 mW。
使用0.18 m CMOS 設計寬頻低雜訊放大器應用於0.7~11.9 GHz，使用閘極與源極變壓器得到輸入寬頻響應，並利用耦合值增加閘極電感，在等效公式上增感的效應會使得高頻轉導能力提升。本電路量測增益為10.3 dB，頻寬為0.8 ~ 9.1 GHz，雜訊指數為4.3 dB，線性度IIP3為0.3 dBm，整體功耗為13.71 mW，面積僅 0.71 × 0.57 mm2。
擬設計之低功耗寬頻直接降頻接收機之頻寬為5~11.7 GHz，在低功耗下取得每個子電路的最佳雜訊指數，接著決定接收機各級之間的阻抗關係，並以電流模態操作。量測轉換增益為35.2 dB，頻寬為3 ~ 11.7 GHz，雙邊帶雜訊為2.47 dB，線性度IIP3為-22.5 dBm，LO-RF 隔離度為-78 dBm，整體功耗為24 mW，面積1.124 × 0.56 mm2。
C/X頻帶寬頻低功耗I/Q直接降頻接收機整合除頻器於單一晶片，利用1/4 LO 責任週期於混頻器，解決IQ交調失真。此直接降頻接收機具有增益線性度三種模態的轉換，量測轉換增益為27.2 dB，頻寬為3 ~ 10 GHz，雙邊帶雜訊為5.9 dB，線性度IIP3為-9 dBm，LO-RF 隔離度為-100 dBm，整體功耗為30.8 mW，面積1.04 × 1 mm2。
;This thesis presents a fully integrated receiver (Rx) front end and low noise amplifiers (LNAs) in tsmcTM 90 nm and 180 nm CMOS technologies. The CMOS RX front end with wideband, low power and low noise is the most challenging circuit due to its low gm, high substrate loss, and low breakdown voltage. Therefore, the main goal of this thesis is to adopt transformer feedback technique to achieve high gm value of the transistor. Meanwhile, the adopted technique also improves the performance in noise figure (NF) and bandwidth. Two LNAs were designed by using gate-source transformer as the wideband matching network which increases the gm value at high frequency regime. The coupling equation of this transformer feedback was derived in this thesis. An inverter type LNA, which has higher gm than CS amplifier, was designed in I-path receiver to obtain a wideband and high integration receiver. The noise contributions of the passive mixer, TIA (Trans-Impedance Amplifier) and the RX front end operated in voltage or current mode are particularly considered to obtain wideband low noise performance. It has to be noted that RC shunt-shunt feedback TIA determines the channel bandwidth of the receiver. After then, the I-path RX front end were integrated into fully integrated I/Q RX front end which was designed by utilizing 25% LO duty cycle to solve the major concerns of the I/Q receiver, i.e., I/Q cross talk and image frequency problems.
The first implemented wideband LNA for C/X band was designed by using gate-source transformer feedback technique in tsmcTM 180 nm CMOS. The transformer feedback technique improves the linearity of the LNA. The measured peak gain and |S11| are 12.04 dB and below -10 dB from 4.5 GHz to 10.1 GHz, respectively. The measured noise figure (NF) and IIP3 are 3.04 dB and 2.5 dBm, respectively. The total power consumption is 9.71 mW.
The second LNA exhibits a wideband performance from 0.7 to 11.9 GHz which was designed an inverter type LNA with a gate-source transformer feedback in tsmcTM 180 nm CMOS. The gm value in the inverter type LNA can be peaked by gate-source transformer feedback topology. The measured peak gain and |S11| are 10.3 dB and below -10 dB from 0.8 GHz to 9.1 GHz, respectively. The measured NF and IIP3 are 4.3 dB and 0.3 dBm, respectively. The power consumption is 13.71 mW. The chip area including pad is 0.71 × 0.57 mm2.
The third design is a low power wideband receiver which integrates an LNA, a Balun, a passive mixer, and a TIA in tsmcTM 90 nm CMOS. These noise contributions of the passive mixer, TIA and the RX front end operated in voltage or current mode are particularly considered to obtain wideband low noise performance. The measured peak conversion gain and |S11| are 35.2 dB and below -10 dB from 3 GHz to 11.7 GHz, respectively. The measured NF and IIP3 are 2.47 dB and -22.5 dBm, respectively. The measured LO to RF isolation is below -78 dB. The total power consumption is only 24 mW. The core chip area is 1.124 × 0.56 mm2.
The fourth design is a low power wideband I/Q receiver which integrated an LNA, a Balun, a pair of I/Q passive mixers, a 25% duty cycle LO and a TIA in tsmcTM 90 nm CMOS. This fully integrated I/Q receiver also provides a three-level gain control by utilizing variable resistors that enhances the linearity performance. The measured peak conversion gain and |S11| are 27.2 dB and below -10 dB from 5 GHz to 10 GHz, respectively. The measured NF and IIP3 are 5.9 dB and -9 dBm, respectively. The measured LO to RF isolation is below -100 dB, The total power consumption is only 30.8 mW. The core chip area is 1.04 × 1 mm2. |
