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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/74877

    Title: 濾波器組多載波系統之 接收端等化器設計與實現;Equalizer Design and Implementation for Filter Bank Multicarrier System
    Authors: 郭淑娜;Guo, Shu-Na
    Contributors: 電機工程學系
    Keywords: 濾波器組;濾波器組多載波;等化器;FBMC;equalizer
    Date: 2017-07-24
    Issue Date: 2017-10-27 16:10:12 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 正交分頻多工器(Orthogonal Frequency Division Multiplexing, OFDM)傳輸技術利用子載波的正交特性及循環字首來消除符元間干擾及載波間干擾,而濾波器組多載波(Filter Bank Multicarrier, FBMC)傳輸系統使用偏移正交振幅調變(Offset Quadrature Amplitude Modulation, OQAM) 以及有良好阻帶衰減的濾波器維持相鄰子載波之間的正交特性,將干擾抑制在相鄰子載波間,並避免循環捲積混疊(circular convolution aliasing) ,因此不使用循環字首也可以消除符元間的干擾,進而也提高了頻寬使用率。
    本論文針對在濾波器組多載波 (Filter Bank Multicarrier, FBMC)系統下的接收端,如何消除符元間干擾與子載波間干擾做分析。並且在WIMAX規格下使用前導符元(Preamble)進行通道估測(Channel Estimation),再使用單一載波頻域等化器對通道效應進行資料回復的補償。等化器的選擇有三種;1.有限脈衝響應單一載波等化器, 2.最小均方根頻域等化器, 3.決策回授等化器。首先,會進行等化器的模擬與比較,然後因為決策反饋等化器能夠比其他等化器以更低的訊雜比通過10-2誤碼率的界線,因此選擇使用決策反饋等化器。電路部分使用Verilog HDL描述,並使用TSMC-90nm製程來實現所設計之電路,最後FPGA驗證其電路設計。
    ;Orthogonal frequency division multiplexing (OFDM) utilizes the quadrature characteristics of the subcarriers and the cyclic prefix to eliminate inter-symbol and inter-carrier interference. Filter bank Multicarrier (FBMC) uses offset quadrature amplitude modulation (OQAM) to maintain the orthogonality between adjacent subcarriers and a filter with good stopband attenuation to avoid the circular convolution aliasing. So the FBMC didn’t need the cyclic prefixes can also eliminate symbols between the interference, leading to higher bandwidth efficiency.
    In this paper, we analyze how to eliminate the inter-symbol interference and inter-carrier interference in the receiver of the FBMC. Channel estimation is performed using the preamble under the WIMAX specification, and the channel effect is compensated using a single carrier frequency domain equalizer. Equalizer has three options: 1. Finite impulse response equalizer. 2. Minimum mean square frequency domain equalizer. 3. Decision feedback equalizer. We would compare those equalizers based on simulation results. The decision feedback equalizer employed since it is able to achieve the 10-2 bit error rate threshold at SNR that is lower than other equalizers. Decision feedback equalizer is descripted with Verilog HDL, and used FPGA to verify its circuit design.
    Appears in Collections:[電機工程研究所] 博碩士論文

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