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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/74986


    題名: 基於高壓製程的高速位準轉換器設計;High speed level shifter design based on high voltage BCD process
    作者: 駱祈宏;Lo, Chi-Hung
    貢獻者: 電機工程學系
    關鍵詞: 位準轉換器設計;整合式雙極性/互補金氧半元件/擴散式金氧半元件;N+深埋層;level-shifter;Bipolar-CMOS-DMOS;N-buried Layer
    日期: 2017-08-24
    上傳時間: 2017-10-27 16:14:57 (UTC+8)
    出版者: 國立中央大學
    摘要: 本論文基於栓鎖式電壓位準轉換電路提出兩種新型適用於高電壓位準轉換器電路架構,並使用高壓製程中的功率電晶體作為電壓隔離器件設計電路。由於功率元件當作高壓隔離開關切換時存在米勒平台效應造成延遲,因此本論文提出利用電阻負載式以及電阻負載稽納二極體式兩種高壓位準轉換器結構,希冀能增加電壓位準轉換的速度。另外,為了解高壓製程中DPW_NBL隔絕環是否在不同逆向偏壓時對轉換器性能造成的影響,在電路中低壓區域的N+深埋層以及高壓區域的N+深埋層分別施以相同以及不同的電壓值以探討差異。為驗正本文提出的位準轉換器架構性能,本論文分別設計並量測三種不同結構的電壓轉換上升電路以電壓轉換下降電路,其中使用TSMC 0.25-um 60-V Bipolar-CMOS-DMOS(BCD) 高壓製程實現高電壓位準轉換器,最後比較轉換器性能以及建立效能指數(FOM)分析。文中所設計的電壓轉換上升位準轉換器可將輸入信號0到5V電壓,頻率為5MHz方波平移為正20V到正25V的方波,總共用於分析比較的七組轉換器整體晶片面積為2603 um X 611um;而電壓轉換下降位準轉換器可將輸入信號0到5V電壓,頻率為5MHz的方波平移為負20V到負25V的方波,7組轉換器整體晶片面積為2595.7 um X 649.4um。;Two novel level-shifter architectures based on cross-coupled latch pairs for high voltage level-shifter applications was proposed and analyzed in this thesis. Since high votlage power transistors were employed as isolated protection devcies inside the level shifters, and the delay caused by Miller effect exists while power transistors switch on and off, two different high voltage level shilfters with resisitive loading and zener diode in series with a resistor, respectively, were designed to increase the transtion speed of the level shifters. In addition, to understand the roles of DPW_NBL isolated ring of the high votlage process while different reverse bias votlage applied with and effects on the performance of the level shifters, the N+ deep burried layer in the low voltage region and the high voltage region, respectively, were applied with the same and different voltage levels, separately, to examine the effects. In order to verify the proposed architectures, three kinds of different high voltage level shifters, including level-shifting from low voltage to high voltage, and high voltage to low voltage, were designed using TSMC 0.25um 60V Bipolar-CMOS-DMOS (BCD) process. The performance matrix (Figure of merit) was built and analyzed. The designed 7 different level-shifter circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a 20 ~ 25V square wave occupy total area of 2603um x 611um, and the other 7 circutis with the capability of shifting a 0 ~ 5V, 5MHz square wave to a -20 ~ -25V square wave occupy the area of 2595.7um x 649.4um, respectively.
    顯示於類別:[電機工程研究所] 博碩士論文

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