以逼零演算法實現無外部校正之單一自適應系統之5 Gbps全速率連續時間線性等化器與決策回授等化器;A 5 Gbps Full-Rate CTLE and DFE Adopting the Single Adaptive System Using Zero-Forcing Algorithm without Off-Chip Calibration

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/77609

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/77609

題名:	以逼零演算法實現無外部校正之單一自適應系統之5 Gbps全速率連續時間線性等化器與決策回授等化器;A 5 Gbps Full-Rate CTLE and DFE Adopting the Single Adaptive System Using Zero-Forcing Algorithm without Off-Chip Calibration
作者:	陳俊諺;Chen, Chun-Yen
貢獻者:	電機工程學系
關鍵詞:	等化器;連續時間線性等化器;決策回授等化器;自適應系統;逼零演算法;Equalizer;CTLE;DFE;Adaptive System;Zero-Forcing Algorithm;LMS Algorithm
日期:	2018-07-16
上傳時間:	2018-08-31 14:49:51 (UTC+8)
出版者:	國立中央大學
摘要:	隨著近年來製程發展以及晶片處理速度日益精進，資料傳遞頻寬皆日漸提升，傳統之並列傳輸方式已被串列傳輸所取代，例如電腦匯流排所使用之DisplayPort、PCI-Express、SATA、USB，或是光纖網路之SONET等規格都皆使用串列傳輸作為傳輸介面。資料通過傳輸通道會受到符碼間干擾的影響導致訊號完整度下降，因此等化器被廣泛應用於接收端以補償資料經過通道所導致的衰減。本論文提出一個採用逼零演算法的自適應系統，可以分別調整連續時間線性等化器(Continuous time linear equalizer, CTLE)以及決策回授等化器(Decision feedback equalizer, DFE)在不同通道衰減下的補償量。傳統上要針對CTLE和DFE進行自適應演算，必須使用兩種不同的自適應回授路徑，因此本論文提出只用一種自適應回授路徑就可以調整這兩種等化器的補償大小，藉此達到降低硬體複雜度與減少整體功率消耗的效果，且由於此自適應系統可以分別對於CTLE以及DFE進行最佳化，所以可以針對更多不同大小的通道衰減進行補償。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS 製程實現，電路操作電壓為1 V，輸入資料速率為5 Gbps，輸入時脈頻率為5 GHz，通道衰減可用範圍為4 dB到27 dB，在通道衰減4 dB時，等化後資料的峰對峰值抖動量為30.22 ps，方均根抖動量為6.54 ps; 在通道衰減17 dB時，等化後資料的峰對峰值抖動量為42.67 ps，方均根抖動量為8.03 ps; 在通道衰減27 dB時，等化後資料的峰對峰值抖動量為56.44 ps，方均根抖動量為10.17 ps。在通道衰減27 dB時之整體功率消耗為12.5 mW，其中CTLE以及DFE之等化器功率消耗為5.5 mW，自適應機制電路之功率消耗為7 mW，晶片面積為1.46 mm2，其中核心電路面積為0.063 mm2。 ;As the quantity demanded of consumer electronics is increasingly grossing, the communication system must be operated at the high speed. Therefore, the high-speed serial link has replaced parallel data buses as dominant input/output (I/O) devices for the data transmission today. However, when the data is transmitted at the high speed, there are heavily attenuated losses on the channel between transmitters (TXs) and receivers (RXs) since the bandwidth of channel is not enhanced. The large channel loss leads the transmitted bit to create the post-cursor in the long tail interfering in the next bit, and then the quality of data is attenuated and increases the bit error rate (BER). This phenomenon is called as the inter-symbol interference (ISI). Therefore, equalizers must be aopted to compensate for the channel loss. This thesis presents an adaptation system with the zero-forcing algorithm to adjust the continuous time linear equalizer (CTLE) and the one-tap decision feedback equalizer (DFE). Conventionally, there are two different adaptation systems to adjust the boost gain and the tap weighting of CTLE and DFE separately, which means that there are two different adaptation loops. Thus, the new adaptation loop which merged two loops of each equalizer types to a single adaptation loop. As a result, the complexity and power consumption of circuits are reduced. Because the flexibility of adaptive equalizers is improved, it can compensate channel losses from 4 dB to 27 dB and operate at the 5-Gbps data rate. The fabricated chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process. When the channel loss is 4 dB, the peak-to-peak jitter of equalized data is 30.22 ps and the root mean square (RMS) jitter is 6.54 ps. When channel loss is 17 dB, the peak-to-peak jitter of equalized data is 45.67 ps and the RMS jitter is 8.03 ps. When channel loss is 27 dB, the peak-to-peak jitter of equalized data is 56.44 ps and the RMS jitter is 10.17 ps. The power consumption is 12.5 mW at a supply voltage of 1 V and the channel loss of 27 dB. The entire equalizer and the overall adaptative system utilize 5.5 mW and 7 mW of power, respectively. The chip area is 1.46 mm2 and the core area is 0.063 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	描述	大小	格式	瀏覽次數
index.html		0Kb	HTML	133	檢視/開啟

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....