隨著行動裝置、電腦網路以及半導體產業日益蓬勃發展，傳統並列傳輸已漸被串列傳輸所取代，並且資料傳遞的速率日漸提升。例如高速串列傳輸技術所使用之PCI-Express、SATA、USB或是光纖網路中的SONET等規格皆已採用串列傳輸作為介面，並且在最新世代規格中，資料傳輸速度甚至到達百億位元每秒等級，因此在電路設計複雜度上也大大提升。 本論文參考USB 3.1 Gen2規格實現一個具資料獨立相位追蹤補償技術之半速率時脈與資料回復電路，並提出相位追蹤補償相位偵測器，針對傳統二進位相位偵測器在高速傳輸下之缺陷做改良。在高速傳輸下，追鎖資料相位變化能力及迴路延遲是影響時脈與資料回復電路效能的重要因素，當輸入資料有連續相同位元時傳統二進位相位偵測器無法判斷領先落後且輸出訊號最小脈波寬度會隨資料速率上升而縮小使得訊號完整度下降，此外，傳統二進位相位偵測器使用同步電路整合訊號邏輯，對減少迴路延遲是一大阻礙。而相位追蹤補償相位偵測器能在輸入資料有連續相同位元下亦能調整還原時脈相位，並使用輸入資料取樣還原時脈來除去同步電路緩解迴路延遲進而提升抖動容忍度。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程，操作電壓為1 V，輸入資料為10 Gbps PRBS7時，還原時脈速率為5 GHz，還原時脈之峰對峰值21.2 pspp，方均根值3.3 psrms，功率消耗為30.1 mW，晶片面積為1.59 mm2，核心電路面積為0.154 mm2。 ;In recent years, according to the rapid development of the process and computers, the series data transmission is widely used for the bus instead of the parallel transmission and the data rate increases progressively, such as PCI-Express, SATA, USB and SONET in the fiber network. The data rate has even risen up to ten billion bits per second in the latest generation specifications. Therefore, the circuit design complexity is greatly increased. This thesis presents a clock and data recovery (CDR) with a data independent phase tracking compensation technique which takes the USB 3.1 Gen2 specification as a reference material. The proposed CDR presents a phase tracking compensation phase detector (PTCPD) which improved the drawback of the conventional bang-bang phase detector (BBPD) in high-speed transmission. When input data has long run situation, the BBPD can’t determine leading or lagging and the minimum pulse width of BBPD output signal will decrease with the increasing of data transmission rate. Above situation will degrade the jitter tolerance (JTOL) and the signal integrity. In addition, the BBPD needs re-timing circuit to integrate signal logic which is an obstacle for reducing the loop latency. The PTCPD can adjust the recovered clock phase in long run situation and use input data sampling recovered clock to remove the re-timing circuit which make JTOL enhanced. The chip is fabricated by a 90 nm standard CMOS process with a supply voltage of 1 V and the input data is 10 Gbps PRBS7 pattern. The measured jitter of the recovered clock is 3.3 psrms, 21.2 pspp, the chip area is 1.59 mm2, the core area is 0.154 mm2 and the total power consumption is 30.1 mW.
