隨著技術的進步，生物醫學領域也經歷了劇烈的變化。近年來，物聯網和可穿戴技術正在以巨大的速度改變著生物醫學設備領域。隨著生物醫學資料如心電圖 (ECG) 監測系統的增加，在面對不同疾病進行診斷時，通常會產生大量的資料。為了儲存這些大量的資料，需要龐大的儲存空間，將導致整個系統的價格非常昂貴。而使用壓縮演算法可以減少儲存空間。本文對一種低功耗的心電圖壓縮方法進行了VLSI實現，壓縮演算法是基於Golomb編碼與自適應性的線性預測方法相結合，Golomb編碼是以熵編碼和線性自適應性方法進行預測工作。本文使用MIT-BIH心律失常資料庫作為輸入資料進行測試，其中包含了兩個身體部位的心電資料，本文使用的壓縮演算法能夠達到2.77 的壓縮倍率，由於該演算法為了減少儲存空間，同時進行了不同的運算，因此在設計硬體設計時可利用此特點以管線化或平行化的方式來減少硬體資源，並運作於高時脈頻率上。本文使用Xilinx Artix-7 FPGA 實現了心電訊號壓縮演算法的設計, 並對 VLSI 設計進行了兩種不同的實現，即時資料處理模式和離線資料處理模式，並使用台積電90nm製程技術進行VLSI設計合成。在即時模式上，可工作在1KHz頻率，其功耗為35.3 nW，而離線模式可工作在 160 MHz頻率，其功耗為10.6mW。;With the recent advancements in technology, the biomedical field has been also going through drastic changes. During recent few years, the internet of things and wearable technologies are changing the biomedical equipment industry at a huge pace. With the increase in biomedical data such as Electrocardiography (ECG) monitoring systems, huge data is normally generated while doing a diagnosis of different diseases. To save this large amount of data, huge storage space is required which results in a higher price of the overall system. This storage space can be reduced by using compression algorithm. In this thesis, VLSI implementation of a low power ECG compression method has been performed. Compression algorithm is based on Golomb Rice coding combined with adaptive linear prediction. Golomb Rice code is working as entropy coding and linear adaption prediction is working as prediction part. For testing purposed, the MIT-BIH Arrhythmia Database has been used as input data which contains two-lead recordings. Compression algorithm is able to achieve a compression ratio of 2.77. As the algorithm is efficient in saving storage space while doing different processes so this benefit has been utilized by designing hardware design which uses less number of resources and works at the high clock frequency. ECG compression algorithm design has been implemented for Xilinx Artix-7 FPGA and two different implementations have been performed for VLSI design i.e. real-time data processing and offline data processing. VLSI design has been synthesized for 90nm technology. Real-time processing works at 1 KHz while offline mode implementation works at 160 MHz. Real-time design consumes 35.3 nW of power while the other design conumes 10.6 mW.
