本論文分別利用tsmcTM 180 nm CMOS及WINTM 250 nm GaN 製程設計寬頻接收機及發射機。論文中共有四顆晶片，其中以CMOS製程進行製作的包含C/X頻段寬頻低雜訊放大器與接收機，而X頻段高功率的功率放大器與混頻器則以GaN製程來進行設計。 利用三線圈組實現C/X 頻段之寬頻低雜訊放大器在元件選用上利用電流密度來進行電晶體尺寸有挑選，並利用PMOS來做為互補式的電晶體達到電路轉導的提升，在輸入端利用源極與閘極的電感形成變壓器來提升電路在高頻的增益，而在輸出端則是採用三線圈組來提升輸出的匹配與增益的平坦度。量測得到增益為11.97 dB，頻寬為0.5 ~ 12.1 GHz，雜訊指數為3.89 dB，線性度IIP3為-2 dBm，整體功耗為12.74 mW，面積僅為0.55×0.68 mm2為現有C/X頻段之寬頻接收機中面積最小的。 應用於C/X頻段之寬頻接收機，採用第一顆的寬頻低雜訊放大器，並利用具有兩個共振點的寬頻巴倫來進行非平衡與平衡的轉換，混頻器部分採用雙平衡的被動混頻器架構能提高本地源與其他端點的隔離度，相較於主動式混頻器沒有而功耗且較適合用於低功耗的設計，在基頻部分利用兩級的轉阻放大器來進行基頻的放大與中頻頻段的定義，並在輸出端加入共模回授來減少製程變異而導致的電壓不匹配。量測轉換增益為26.8 dB，頻寬為4.1 ~ 11.7 GHz，雙邊帶雜訊指數為6.3 dB，線性度IIP3為-14.4 dBm，整體功耗為31.89 mW。 具2.37 W輸出功率之氮化鎵功率放大器應用於X頻段，利用一推二的方式來提升功率放大器的增益，在穩定度部分利用串聯RC與並聯RL來提升電路的穩定度，其中並聯RL在電路給與偏壓時能減少使用過大的電阻而導致的直流偏移的問題，在輸出端採用低阻抗的傳輸線來進行二元功率結合以減少輸出端的損耗。量測增益為14.07 dB，頻寬為8.55 ~ 13.9 GHz，輸出功率1-dB壓縮點為29.3 dBm，飽和輸出功率為33.75 dBm，功率附加效益為19.57%。 應用於X頻段之氮化鎵次諧波電阻式混頻器，在本地源端利用電容、電感元件取代傳統馬遜巴倫大幅地降低晶片的使用面積，在電晶體的尺寸挑選利用輸出功率與本地源所需功率的取捨來進行最佳化挑選，因採用次諧波來進行混頻能減少本地源的所需的頻率與功率，並考量大信號操作下電路的阻抗變化與增益擴張的現象，大幅降低本地源所需的輸入功率，且本電路為單端輸入輸出，所以不須額外的巴倫較適合用於系統的整合。模擬轉換損耗為11.73 dB，頻寬為9.05 ~ 11.25 GHz，輸出功率1-dB壓縮點為2.62 dBm，本地源所需功率為5 dBm。 ;This thesis presents a wideband receiver (Rx) front-end and transmitter (Tx) in tsmcTM 180 nm and WINTM 250 nm GaN technologies. Four chips including C/X band wideband low-noise amplifiers and receivers are designed and fabricated in CMOS process. X band high power amplifier and mixer are designed and implemented in 250 nm GaN process. The first chip is a wideband low noise amplifier (LNA) which was designed by using gate-source transformer and complementary transistors, which has higher gm than that of common source amplifier. The second stage is designed using a trifilar transformer which coupled the gate, source and drain inductors to reduce the chip size and provide wideband output matching. The measured peak gain is 11.97 dB over a 3-dB bandwidth from 0.5 to 12.1 GHz with minimum noise figure (NF) of 3.89 dB. The measured P1dB is -12 dBm and IIP3 is -2 dBm. The total power consumption is 12.74 mW. The chip size is only 0.55×0.68 mm2. The second chip is a C/X band receiver which integrated previous LNA, a balun, a mixer and a trans-impedance amplifier (TIA). The balun is an inductively coupled resonator to provide wideband unbalanced to balanced transformation. The mixer was designed with as passive double balanced topology to enhance the LO/RF isolation with no power consumption. A two-stage TIA was used as baseband amplifier to increase the gain in receive chain. In addition, the TIA with RC shunt feedback can define the channel bandwidth of the receiver. The measured peak conversion gain is26.8 dB over a 3-dB bandwidth from 4.1 to 11.7 GHz with minimum double-sideband noise figure (NFdSB) of 6.3 dB. The measured P1dB is -24 dBm and IIP3 is -14.4dBm. The total power consumption is 31.89 mW. The chip size is 1.313 ×0.831 mm2. The third chip is a GaN high power amplifier (HPA). The HPA was used low impedance transmission line to reduce loss of the output stage. The analysis of the oscillation regarding even and odd mode was conducted. The HPA was added appropriate components to prevent the oscillations. The measured peak gain is 14.07 dB over a 3-dB bandwidth from 8.55 to 13.9 GHz. The measured OP1dB is -29.3 dBm and Psat is 33.75 dBm. The measured power added efficiency is 19.57 %. The chip size is 2.24×1.736 mm2. The fourth chip is a sub-harmonic resistive mixer which adopted a lumped element Marchand Balun to reduce the chip size. The properly selections the transistor size and bias conditions make the sub-harmonic mixer operate at low LO power with high output power. The conversion loss of the mixer is 11.73 dB over a 3-dB bandwidth from 9.05 to 11.25 GHz. The simulated OP1dB is 2.62 dBm under LO power of 5 dBm. The chip size is 2.24×1.736 mm2.
