選擇性磊晶成長砷化銦鎵與砷化銦鋁於奈米圖案化鍺模板;Selective Area Epitaxy of InGaAs and AlInAs on Nano-Patterned Ge Templates

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题名:	選擇性磊晶成長砷化銦鎵與砷化銦鋁於奈米圖案化鍺模板;Selective Area Epitaxy of InGaAs and AlInAs on Nano-Patterned Ge Templates
作者:	陳泰霖;Chen, Tai-Lin
贡献者:	電機工程學系
关键词:	砷化銦鎵;鍺;選擇性磊晶;InGaAs;Ge;Selective Area Epitaxy
日期:	2019-01-28
上传时间:	2019-04-02 15:08:00 (UTC+8)
出版者:	國立中央大學
摘要:	互補式金氧半(CMOS)積體電路遵循著摩爾定律(Moore Law)持續微縮電晶體尺寸，在過去數十年的進步已微縮至七奈米技術節點，如何在一定的成本之下，持續提升積體電路的特性並降低其功耗一直是微電子界眾人所關心的議題。目前國際上提出了兩個大方向來尋求突破，一是使用創新的元件結構，另其則是導入新穎的通道材料。在眾多的新材料中，鍺的電洞遷移率較矽為高，被認為最適合取代矽來作為P型通道材料，而具有高電子遷移率的III-V族化合物半導體則可被應用在N型通道電晶體中。為此，將此二種異質材料整合在十二吋矽晶圓上是達成量產規模之選項之一，也成為國際各界積極研發之關鍵技術。本研究採取的異質整合策略是以有機金屬化學蒸氣沉積法選擇性磊晶成長III-V族化合物半導體，即砷化銦鎵和砷化銦鋁，於具有奈米圖案之鍺模板上。此鍺模板上的鍺薄膜是以化學蒸氣沉積法磊晶於(100)的矽基板上。本論文研究探討模板圖案蝕刻形貌以及基板溫度、V/III族氣體流量比、磊晶速度等成長條件對磊晶形貌與材料品質之影響，並選擇適當磊晶參數成功整合砷化铟鎵與鍺之鰭狀奈米線(80 nm)於矽基板上。 ;Complementary Metal-Oxide-Semiconductor integrated circuit follow Moore′s Law by decreasing transistor size consistently. With progress in the past few decades,it reach 7nm technology node. How to improve the performace and reduce its power consumption under certain cost has always be a topic in the industry. At present, two major approaches have been proposed to seek breakthroughs internationally. One is to use innovative component structures, and the other is to introduce novel channel materials. Among the proposed materials, high hole mobility Ge and high electron mobility InGaAs has been considered to be the most promising channel materials for p-channel and n-channel MOSFETs, respectively. Therefore,one of the options is the integration of two heterogeneous materials on the 12-inch silicon wafer,and the technique can be the most critical method that industry highly keen to do more research and wider development. The heterogeneous integration strategy in the study is to selective area epitaxy of InGaAs and AlInAs on nano-patterned Ge templates by metal-organic chemical vapor deposition (MOCVD). Ge film is epitaxially on a (100) silicon substrate by chemical vapor deposition. This dissertation aims to investigate the effect of different Ge templates profile and epitaxy growth parameter like growth temperature, V/III ratio and growth rate to epitaxy layer quality and morphology, and choose appropriate epitaxy parameter to integrate the InGaAs and Ge fin nanowire on the Si substrate successfully.
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