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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/81490


    Title: 互補式金氧半導體Ku頻段寬頻功率放大器與K頻段開關鍵控發射機暨X頻段氮化鎵瓦特級功率放大器之研製;Implementations on CMOS Ku-band Wideband Power Amplifier, K-band On-Off Keying Transmitter and X-band GaN Watt-level Power Amplifiers
    Authors: 黃禮賢;Huang, Li-Hsien
    Contributors: 電機工程學系
    Keywords: 功率放大器;發射機;瓦特級功率放大器;Power Amplifier;Transmitter;Watt-level Power Amplifier
    Date: 2019-08-19
    Issue Date: 2019-09-03 15:57:02 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本篇論文共分為五個章節,論文包含使用 tsmcTM 提供的 0.18-µm CMOS、90-nm CMOS 與 WINTM 提供的 0.25-µm GaN 製程,實現應用於 Ku 頻段之寬頻功率放大器、應用於 K 頻段無線感測網路之開關鍵控發射機以及應用於 X 頻段軍用海事雷達之瓦特級功率放大器。

    第二章提出採用磁耦合變壓器於 CMOS 功率放大器之研究,為解決 0.18-µm CMOS 製程在 Ku 至 Ka 頻段中所遇到之瓶頸,如基板損耗過大、轉導能力不佳與電晶體崩潰電壓過低等問題,利用達靈頓對結合疊接架構同時提升電流截止頻率 (fT) 與電晶體轉導能力 (gm),使得低階製程能夠在毫米波頻段下獲得足夠的增益及效率,同時也利用交錯耦合回授電容改善電路的增益及頻寬。量測結果顯示小訊號增益最高為 14 dB,飽和輸出功率為 22.2 dBm,1-dB 增益壓縮點輸出功率為 18.8 dBm,功率附加效率最高可達 15.8%,3-dB 頻寬為 6 GHz (11.3 GHz 至 17.3 GHz),晶片面積為 0.7 (1.46×0.48) mm2。

    第三章提出應用於無線感測網路之 K 頻段開關鍵控發射機,晶片採用 90-nm CMOS製程。本章節的發射機架構是由 24 GHz 壓控振盪器產生訊號後,經變壓器將訊號耦合給予緩衝器放大,並且透過後端的調變器送出高資料傳輸率的調變訊號,最後利用小型功率放大器將訊號放大並且推送出去,實現低消耗功率且高資料傳輸率之發射機電路。量測結果顯示其可調頻率範圍從 22.7 GHz 至 25.4 GHz,在位移頻率為 1 MHz 時,最低相位雜訊為 -101.6 dBc/Hz,最大輸出功率為 5.3 dBm,最低消耗功率為 23 mW,當數據速率為 2.4 Gbps,換算之能量效率為 9.6 pJ/bit,晶片面積為 0.36 (0.9×0.4) mm2。

    第四章提出應用於軍用海事雷達之 X 頻段瓦特級功率放大器,章節 4-3 電路採用兩級共源級架構,輸出端利用低損耗與超緊湊之四路合併結合器以達到十瓦的輸出功率。量測結果顯示功率增益最高為 20.6 dB,飽和輸出功率為 41.73 dBm (14.9 W),1-dB 增益壓縮點輸出功率為 30.9 dBm,功率附加效率最高可達 37%,功率面積比和功率密度分別為 4.29 W/mm2、4.66 W/mm,晶片面積為 3.49 (2.1×1.66) mm2。章節 4-4 電路採用兩級共源級架構,輸出端利用諧波調諧網路改善線性度、效率與相鄰通道洩漏比,同時也將兩路功率合併以增加輸出功率。結果顯示功率增益最高為 19.8 dB,飽和輸出功率為 38.44 dBm (7 W),1-dB 增益壓縮點輸出功率為 36.9 dBm,功率附加效率最高可達 45.4%,功率面積比和功率密度分別為 2.77 W/mm2、4.36 W/mm,晶片面積為 2.52 (2.63×0.96) mm2。
    ;This thesis consists of five chapters. The thesis developed a Ku-band wideband power amplifier and a K-band on-off keying (OOK) transmitter for wireless sensor network (WSN) applications in tsmcTM 0.18-µm CMOS process and 90-nm CMOS process, respectively. The author also developed two watt-level power amplifiers for X-band military marine radar in WINTM 0.25-µm GaN process.

    Chapter 2 presents a Ku-band neutralized Darlington cascode power amplifier by using transformer-coupled matching in 0.18-µm CMOS. To solve the bottleneck of the 0.18-μm CMOS process in millimeter wave, such as lossy substrate, poor capability of transconductance (gm) and low breakdown voltage. Darlington pair with cascode topology was adopted as power cell to enhance the current cut-off frequency (fT), maximum oscillation frequency (fmax) and maximum available gain (MAG) of the transistors for being capable of operating at Ku-band to Ka-band. This design also used the cross-coupled capacitors to improve gain and bandwidth. The measurement results showed that the amplifier achieved a peak gain of 14 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 22.2 dBm and 18.8 dBm, respectively. The peak power added efficiency (PAE_max) is 15.8%. The 3-dB bandwidth is from 11.3 to 17.3 GHz. The chip area is 0.7 (1.46×0.48) mm2.

    Chapter 3 proposes a high energy-efficiency K-band OOK transmitter in 90-nm CMOS process. This chapter improves the drawback that conventional transmitter cannot apply the proper modulation signal at buffer stage. The modified transmitter consists of a wideband voltage control oscillator (VCO), a high isolation and high data rate switch-type modulator and a medium power amplifier. The measurement results showed that the OOK transmitter achieves a frequency tuning range from 22.7 to 25.4 GHz, a minimum phase noise of -101.6 dBc/Hz at 1-MHz offset and a maximum output power of 5.3 dBm. The total power consumption is 23 mW. When the data rate is 2.4 Gbps, the energy efficiency is 9.6 pJ/bit. The chip area is 0.36 (0.9×0.4) mm2.

    Chapter 4 proposes two types of watt-level power amplifier that applied to X-band military marine radar. The chapter 4-3 presents a power amplifier using two-stage configuration to achieve a linear gain of above 20 dB. In order to achieve 10 W output power and having excellent power per area ratio (PPAR), an ultra-compact layout of four-way power combining structure has been developed. The measurement results showed that the power amplifier achieves a peak power gain of 20.6 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 41.73 dBm (14.9 W) and 30.9 dBm, respectively. The peak power added efficiency (PAE_max) is 37%. The PPAR and power density are 4.29 W/mm2 and 4.66 W/mm, respectively. The chip area is 3.49 (2.1×1.66) mm2. The chapter 4-4 presents a high efficient power amplifier using two-stage configuration to achieve a linear gain of 20 dB. A compact harmonic tuning network was adopted to improve the linearity and efficiency. Also satisfy the stringent adjacent channel leakage ratio (ACLR) requirements. The designed power amplifier achieves a peak power gain of 19.8 dB, a saturated output power (P_sat) and output power of 1-dB gain compression point (OP_1dB) of 38.4 dBm (7 W) and 36.9 dBm, respectively. The peak power added efficiency (PAE_max) is 45.4%. The PPAR and power density are 2.77 W/mm2 and 4.36 W/mm, respectively. The chip area is 2.52 (2.63×0.96) mm2.
    Appears in Collections:[電機工程研究所] 博碩士論文

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